net: mscc: describe the PTP register range
This patch adds support for using the PTP register range, and adds a description of its registers. This bank is used when configuring PTP. Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -23,6 +23,7 @@
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#include "ocelot_sys.h"
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#include "ocelot_sys.h"
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#include "ocelot_qs.h"
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#include "ocelot_qs.h"
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#include "ocelot_tc.h"
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#include "ocelot_tc.h"
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#include "ocelot_ptp.h"
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#define PGID_AGGR 64
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#define PGID_AGGR 64
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#define PGID_SRC 80
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#define PGID_SRC 80
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@ -71,6 +72,7 @@ enum ocelot_target {
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SYS,
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SYS,
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S2,
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S2,
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HSIO,
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HSIO,
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PTP,
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TARGET_MAX,
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TARGET_MAX,
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};
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};
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@ -343,6 +345,13 @@ enum ocelot_reg {
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S2_CACHE_ACTION_DAT,
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S2_CACHE_ACTION_DAT,
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S2_CACHE_CNT_DAT,
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S2_CACHE_CNT_DAT,
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S2_CACHE_TG_DAT,
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S2_CACHE_TG_DAT,
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PTP_PIN_CFG = PTP << TARGET_OFFSET,
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PTP_PIN_TOD_SEC_MSB,
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PTP_PIN_TOD_SEC_LSB,
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PTP_PIN_TOD_NSEC,
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PTP_CFG_MISC,
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PTP_CLK_CFG_ADJ_CFG,
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PTP_CLK_CFG_ADJ_FREQ,
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};
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};
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enum ocelot_regfield {
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enum ocelot_regfield {
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@ -182,6 +182,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
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struct {
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struct {
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enum ocelot_target id;
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enum ocelot_target id;
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char *name;
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char *name;
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u8 optional:1;
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} res[] = {
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} res[] = {
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{ SYS, "sys" },
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{ SYS, "sys" },
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{ REW, "rew" },
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{ REW, "rew" },
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@ -189,6 +190,7 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
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{ ANA, "ana" },
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{ ANA, "ana" },
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{ QS, "qs" },
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{ QS, "qs" },
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{ S2, "s2" },
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{ S2, "s2" },
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{ PTP, "ptp", 1 },
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};
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};
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if (!np && !pdev->dev.platform_data)
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if (!np && !pdev->dev.platform_data)
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@ -205,8 +207,14 @@ static int mscc_ocelot_probe(struct platform_device *pdev)
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struct regmap *target;
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struct regmap *target;
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target = ocelot_io_platform_init(ocelot, pdev, res[i].name);
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target = ocelot_io_platform_init(ocelot, pdev, res[i].name);
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if (IS_ERR(target))
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if (IS_ERR(target)) {
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if (res[i].optional) {
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ocelot->targets[res[i].id] = NULL;
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continue;
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}
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return PTR_ERR(target);
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return PTR_ERR(target);
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}
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ocelot->targets[res[i].id] = target;
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ocelot->targets[res[i].id] = target;
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}
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}
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@ -0,0 +1,41 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/*
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* Microsemi Ocelot Switch driver
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*
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* License: Dual MIT/GPL
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* Copyright (c) 2017 Microsemi Corporation
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*/
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#ifndef _MSCC_OCELOT_PTP_H_
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#define _MSCC_OCELOT_PTP_H_
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#define PTP_PIN_CFG_RSZ 0x20
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#define PTP_PIN_TOD_SEC_MSB_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_TOD_SEC_LSB_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_TOD_NSEC_RSZ PTP_PIN_CFG_RSZ
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#define PTP_PIN_CFG_DOM BIT(0)
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#define PTP_PIN_CFG_SYNC BIT(2)
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#define PTP_PIN_CFG_ACTION(x) ((x) << 3)
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#define PTP_PIN_CFG_ACTION_MASK PTP_PIN_CFG_ACTION(0x7)
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enum {
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PTP_PIN_ACTION_IDLE = 0,
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PTP_PIN_ACTION_LOAD,
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PTP_PIN_ACTION_SAVE,
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PTP_PIN_ACTION_CLOCK,
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PTP_PIN_ACTION_DELTA,
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PTP_PIN_ACTION_NOSYNC,
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PTP_PIN_ACTION_SYNC,
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};
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#define PTP_CFG_MISC_PTP_EN BIT(2)
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#define PSEC_PER_SEC 1000000000000LL
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#define PTP_CFG_CLK_ADJ_CFG_ENA BIT(0)
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#define PTP_CFG_CLK_ADJ_CFG_DIR BIT(1)
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#define PTP_CFG_CLK_ADJ_FREQ_NS BIT(30)
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#endif
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@ -234,6 +234,16 @@ static const u32 ocelot_s2_regmap[] = {
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REG(S2_CACHE_TG_DAT, 0x000388),
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REG(S2_CACHE_TG_DAT, 0x000388),
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};
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};
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static const u32 ocelot_ptp_regmap[] = {
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REG(PTP_PIN_CFG, 0x000000),
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REG(PTP_PIN_TOD_SEC_MSB, 0x000004),
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REG(PTP_PIN_TOD_SEC_LSB, 0x000008),
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REG(PTP_PIN_TOD_NSEC, 0x00000c),
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REG(PTP_CFG_MISC, 0x0000a0),
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REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4),
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REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8),
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};
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static const u32 *ocelot_regmap[] = {
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static const u32 *ocelot_regmap[] = {
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[ANA] = ocelot_ana_regmap,
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[ANA] = ocelot_ana_regmap,
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[QS] = ocelot_qs_regmap,
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[QS] = ocelot_qs_regmap,
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@ -241,6 +251,7 @@ static const u32 *ocelot_regmap[] = {
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[REW] = ocelot_rew_regmap,
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[REW] = ocelot_rew_regmap,
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[SYS] = ocelot_sys_regmap,
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[SYS] = ocelot_sys_regmap,
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[S2] = ocelot_s2_regmap,
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[S2] = ocelot_s2_regmap,
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[PTP] = ocelot_ptp_regmap,
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};
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};
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static const struct reg_field ocelot_regfields[] = {
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static const struct reg_field ocelot_regfields[] = {
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