[IA64-SGI] disable TIOCA GART TLB prefetching
Patch to disable SGI TIOCA GART TLB prefetching due to hw bug. Signed-off-by: Mark Maule <maule@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
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@ -171,15 +171,15 @@ tioca_gart_init(struct tioca_kernel *tioca_kern)
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* use agp op-combining
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* use agp op-combining
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* use GET semantics to fetch memory
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* use GET semantics to fetch memory
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* participate in coherency domain
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* participate in coherency domain
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* prefetch TLB entries
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* DISABLE GART PREFETCHING due to hw bug tracked in SGI PV930029
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*/
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*/
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ca_base->ca_control1 |= CA_AGPDMA_OP_ENB_COMBDELAY; /* PV895469 ? */
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ca_base->ca_control1 |= CA_AGPDMA_OP_ENB_COMBDELAY; /* PV895469 ? */
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ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
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ca_base->ca_control2 &= ~(CA_GART_MEM_PARAM);
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ca_base->ca_control2 |= (0x2ull << CA_GART_MEM_PARAM_SHFT);
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ca_base->ca_control2 |= (0x2ull << CA_GART_MEM_PARAM_SHFT);
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tioca_kern->ca_gart_iscoherent = 1;
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tioca_kern->ca_gart_iscoherent = 1;
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ca_base->ca_control2 |=
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ca_base->ca_control2 &=
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(CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
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~(CA_GART_WR_PREFETCH_ENB | CA_GART_RD_PREFETCH_ENB);
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/*
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/*
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* Unmask GART fetch error interrupts. Clear residual errors first.
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* Unmask GART fetch error interrupts. Clear residual errors first.
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