mmc: mmci: add stm32 sdmmc variant
This patch adds a stm32 sdmmc variant, rev 1.1. Introduces a new Manufacturer id "0x53, ascii 'S' to define new stm32 sdmmc family with clean range of amba revision/configurations bits (corresponding to sdmmc_ver register with major/minor fields). Add 2 variants properties: -dma_lli, to enable link list support. -stm32_idmabsize_mask, defines the range of SDMMC_IDMABSIZER register which specify the number bytes per buffer. DT properties for sdmmc: -Indicate signal directions (only one property for d0dir, d123dir, cmd_dir) -Select command and data phase relation. -Select "clock in" from an external driver. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Ludovic Barre
Ulf Hansson
parent
62022894cd
commit
46b723dd86
@ -34,6 +34,16 @@ config MMC_QCOM_DML
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if unsure, say N.
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config MMC_STM32_SDMMC
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bool "STMicroelectronics STM32 SDMMC Controller"
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depends on MMC_ARMMMCI
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default y
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help
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This selects the STMicroelectronics STM32 SDMMC host controller.
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If you have a STM32 sdmmc host with internal DMA say Y here.
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If unsure, say N.
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config MMC_PXA
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tristate "Intel PXA25x/26x/27x Multimedia Card Interface support"
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depends on ARCH_PXA
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@ -6,6 +6,7 @@
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obj-$(CONFIG_MMC_ARMMMCI) += armmmci.o
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armmmci-y := mmci.o
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armmmci-$(CONFIG_MMC_QCOM_DML) += mmci_qcom_dml.o
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armmmci-$(CONFIG_MMC_STM32_SDMMC) += mmci_stm32_sdmmc.o
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obj-$(CONFIG_MMC_PXA) += pxamci.o
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obj-$(CONFIG_MMC_MXC) += mxcmmc.o
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obj-$(CONFIG_MMC_MXS) += mxs-mmc.o
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@ -52,6 +52,12 @@ void mmci_variant_init(struct mmci_host *host);
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static inline void mmci_variant_init(struct mmci_host *host) {}
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#endif
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#ifdef CONFIG_MMC_STM32_SDMMC
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void sdmmc_variant_init(struct mmci_host *host);
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#else
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static inline void sdmmc_variant_init(struct mmci_host *host) {}
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#endif
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static unsigned int fmax = 515633;
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static struct variant_data variant_arm = {
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@ -259,6 +265,25 @@ static struct variant_data variant_stm32 = {
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.init = mmci_variant_init,
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};
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static struct variant_data variant_stm32_sdmmc = {
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.fifosize = 16 * 4,
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.fifohalfsize = 8 * 4,
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.f_max = 208000000,
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.stm32_clkdiv = true,
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.cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
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.cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
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.cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
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.cmdreg_srsp = MCI_CPSM_STM32_SRSP,
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.data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
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.irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
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.datactrl_first = true,
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.datacnt_useless = true,
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.datalength_bits = 25,
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.datactrl_blocksz = 14,
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.stm32_idmabsize_mask = GENMASK(12, 5),
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.init = sdmmc_variant_init,
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};
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static struct variant_data variant_qcom = {
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.fifosize = 16 * 4,
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.fifohalfsize = 8 * 4,
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@ -1736,6 +1761,12 @@ static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
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host->pwr_reg_add |= MCI_ST_CMDDIREN;
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if (of_get_property(np, "st,sig-pin-fbclk", NULL))
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host->pwr_reg_add |= MCI_ST_FBCLKEN;
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if (of_get_property(np, "st,sig-dir", NULL))
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host->pwr_reg_add |= MCI_STM32_DIRPOL;
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if (of_get_property(np, "st,neg-edge", NULL))
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host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
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if (of_get_property(np, "st,use-ckin", NULL))
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host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
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if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
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mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
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@ -2177,6 +2208,11 @@ static const struct amba_id mmci_ids[] = {
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.mask = 0x00ffffff,
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.data = &variant_stm32,
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},
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{
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.id = 0x10153180,
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.mask = 0xf0ffffff,
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.data = &variant_stm32_sdmmc,
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},
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/* Qualcomm variants */
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{
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.id = 0x00051180,
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@ -304,6 +304,8 @@ struct mmci_host;
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* @start_err: bitmask identifying the STARTBITERR bit inside MMCISTATUS
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* register.
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* @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register
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* @dma_lli: true if variant has dma link list feature.
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* @stm32_idmabsize_mask: stm32 sdmmc idma buffer size.
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*/
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struct variant_data {
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unsigned int clkreg;
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@ -346,6 +348,8 @@ struct variant_data {
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unsigned int irq_pio_mask;
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u32 start_err;
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u32 opendrain;
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u8 dma_lli:1;
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u32 stm32_idmabsize_mask;
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void (*init)(struct mmci_host *host);
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};
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@ -387,6 +391,7 @@ struct mmci_host {
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u32 pwr_reg;
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u32 pwr_reg_add;
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u32 clk_reg;
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u32 clk_reg_add;
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u32 datactrl_reg;
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u32 busy_status;
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u32 mask1_reg;
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282
drivers/mmc/host/mmci_stm32_sdmmc.c
Normal file
282
drivers/mmc/host/mmci_stm32_sdmmc.c
Normal file
@ -0,0 +1,282 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2018 - All Rights Reserved
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* Author: Ludovic.barre@st.com for STMicroelectronics.
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*/
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/card.h>
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#include <linux/reset.h>
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#include <linux/scatterlist.h>
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#include "mmci.h"
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#define SDMMC_LLI_BUF_LEN PAGE_SIZE
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#define SDMMC_IDMA_BURST BIT(MMCI_STM32_IDMABNDT_SHIFT)
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struct sdmmc_lli_desc {
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u32 idmalar;
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u32 idmabase;
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u32 idmasize;
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};
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struct sdmmc_priv {
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dma_addr_t sg_dma;
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void *sg_cpu;
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};
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int sdmmc_idma_validate_data(struct mmci_host *host,
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struct mmc_data *data)
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{
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struct scatterlist *sg;
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int i;
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/*
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* idma has constraints on idmabase & idmasize for each element
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* excepted the last element which has no constraint on idmasize
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*/
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for_each_sg(data->sg, sg, data->sg_len - 1, i) {
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if (!IS_ALIGNED(sg_dma_address(data->sg), sizeof(u32)) ||
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!IS_ALIGNED(sg_dma_len(data->sg), SDMMC_IDMA_BURST)) {
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dev_err(mmc_dev(host->mmc),
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"unaligned scatterlist: ofst:%x length:%d\n",
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data->sg->offset, data->sg->length);
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return -EINVAL;
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}
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}
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if (!IS_ALIGNED(sg_dma_address(data->sg), sizeof(u32))) {
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dev_err(mmc_dev(host->mmc),
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"unaligned last scatterlist: ofst:%x length:%d\n",
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data->sg->offset, data->sg->length);
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return -EINVAL;
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}
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return 0;
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}
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static int _sdmmc_idma_prep_data(struct mmci_host *host,
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struct mmc_data *data)
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{
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int n_elem;
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n_elem = dma_map_sg(mmc_dev(host->mmc),
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data->sg,
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data->sg_len,
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mmc_get_dma_dir(data));
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if (!n_elem) {
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dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
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return -EINVAL;
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}
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return 0;
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}
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static int sdmmc_idma_prep_data(struct mmci_host *host,
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struct mmc_data *data, bool next)
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{
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/* Check if job is already prepared. */
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if (!next && data->host_cookie == host->next_cookie)
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return 0;
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return _sdmmc_idma_prep_data(host, data);
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}
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static void sdmmc_idma_unprep_data(struct mmci_host *host,
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struct mmc_data *data, int err)
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{
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dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
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mmc_get_dma_dir(data));
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}
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static int sdmmc_idma_setup(struct mmci_host *host)
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{
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struct sdmmc_priv *idma;
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idma = devm_kzalloc(mmc_dev(host->mmc), sizeof(*idma), GFP_KERNEL);
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if (!idma)
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return -ENOMEM;
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host->dma_priv = idma;
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if (host->variant->dma_lli) {
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idma->sg_cpu = dmam_alloc_coherent(mmc_dev(host->mmc),
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SDMMC_LLI_BUF_LEN,
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&idma->sg_dma, GFP_KERNEL);
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if (!idma->sg_cpu) {
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dev_err(mmc_dev(host->mmc),
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"Failed to alloc IDMA descriptor\n");
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return -ENOMEM;
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}
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host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
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sizeof(struct sdmmc_lli_desc);
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host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
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} else {
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host->mmc->max_segs = 1;
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host->mmc->max_seg_size = host->mmc->max_req_size;
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}
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return 0;
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}
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static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
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{
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struct sdmmc_priv *idma = host->dma_priv;
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struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu;
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struct mmc_data *data = host->data;
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struct scatterlist *sg;
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int i;
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if (!host->variant->dma_lli || data->sg_len == 1) {
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writel_relaxed(sg_dma_address(data->sg),
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host->base + MMCI_STM32_IDMABASE0R);
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writel_relaxed(MMCI_STM32_IDMAEN,
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host->base + MMCI_STM32_IDMACTRLR);
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return 0;
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}
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for_each_sg(data->sg, sg, data->sg_len, i) {
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desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc);
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desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS
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| MMCI_STM32_ABR;
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desc[i].idmabase = sg_dma_address(sg);
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desc[i].idmasize = sg_dma_len(sg);
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}
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/* notice the end of link list */
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desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA;
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dma_wmb();
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writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
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writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
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writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
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writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
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writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
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host->base + MMCI_STM32_IDMACTRLR);
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return 0;
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}
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static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
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{
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writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
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}
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static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
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{
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unsigned int clk = 0, ddr = 0;
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if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
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host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
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ddr = MCI_STM32_CLK_DDR;
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/*
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* cclk = mclk / (2 * clkdiv)
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* clkdiv 0 => bypass
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* in ddr mode bypass is not possible
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*/
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if (desired) {
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if (desired >= host->mclk && !ddr) {
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host->cclk = host->mclk;
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} else {
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clk = DIV_ROUND_UP(host->mclk, 2 * desired);
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if (clk > MCI_STM32_CLK_CLKDIV_MSK)
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clk = MCI_STM32_CLK_CLKDIV_MSK;
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host->cclk = host->mclk / (2 * clk);
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}
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} else {
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/*
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* while power-on phase the clock can't be define to 0,
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* Only power-off and power-cyc deactivate the clock.
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* if desired clock is 0, set max divider
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*/
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clk = MCI_STM32_CLK_CLKDIV_MSK;
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host->cclk = host->mclk / (2 * clk);
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}
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/* Set actual clock for debug */
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if (host->mmc->ios.power_mode == MMC_POWER_ON)
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host->mmc->actual_clock = host->cclk;
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else
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host->mmc->actual_clock = 0;
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if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
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clk |= MCI_STM32_CLK_WIDEBUS_4;
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if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
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clk |= MCI_STM32_CLK_WIDEBUS_8;
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clk |= MCI_STM32_CLK_HWFCEN;
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clk |= host->clk_reg_add;
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clk |= ddr;
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/*
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* SDMMC_FBCK is selected when an external Delay Block is needed
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* with SDR104.
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*/
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if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50) {
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clk |= MCI_STM32_CLK_BUSSPEED;
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if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) {
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clk &= ~MCI_STM32_CLK_SEL_MSK;
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clk |= MCI_STM32_CLK_SELFBCK;
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}
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}
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mmci_write_clkreg(host, clk);
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}
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static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
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{
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struct mmc_ios ios = host->mmc->ios;
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pwr = host->pwr_reg_add;
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if (ios.power_mode == MMC_POWER_OFF) {
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/* Only a reset could power-off sdmmc */
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reset_control_assert(host->rst);
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udelay(2);
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reset_control_deassert(host->rst);
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/*
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* Set the SDMMC in Power-cycle state.
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* This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK
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* are driven low, to prevent the Card from being supplied
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* through the signal lines.
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*/
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mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
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} else if (ios.power_mode == MMC_POWER_ON) {
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/*
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* After power-off (reset): the irq mask defined in probe
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* functionis lost
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* ault irq mask (probe) must be activated
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*/
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writel(MCI_IRQENABLE | host->variant->start_err,
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host->base + MMCIMASK0);
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/*
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* After a power-cycle state, we must set the SDMMC in
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* Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are
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* driven high. Then we can set the SDMMC to Power-on state
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*/
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mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
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mdelay(1);
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mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
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}
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}
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static struct mmci_host_ops sdmmc_variant_ops = {
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.validate_data = sdmmc_idma_validate_data,
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.prep_data = sdmmc_idma_prep_data,
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.unprep_data = sdmmc_idma_unprep_data,
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.dma_setup = sdmmc_idma_setup,
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.dma_start = sdmmc_idma_start,
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.dma_finalize = sdmmc_idma_finalize,
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.set_clkreg = mmci_sdmmc_set_clkreg,
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.set_pwrreg = mmci_sdmmc_set_pwrreg,
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};
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void sdmmc_variant_init(struct mmci_host *host)
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{
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host->ops = &sdmmc_variant_ops;
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}
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