CRIS: remove SMP code
The CRIS SMP code cannot be built since there is no (and appears to never have been) a CONFIG_SMP Kconfig option in arch/cris/. Remove it. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Jesper Nilsson <jespern@axis.com>
This commit is contained in:
Rabin Vincent
Jesper Nilsson
parent
06aca92424
commit
47a8f6fb34
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@ -46,7 +46,6 @@ config CRIS
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select ARCH_WANT_IPC_PARSE_VERSION
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select GENERIC_IRQ_SHOW
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select GENERIC_IOMAP
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select GENERIC_SMP_IDLE_THREAD if ETRAX_ARCH_V32
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select GENERIC_CMOS_UPDATE
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select MODULES_USE_ELF_RELA
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select CLONE_BACKWARDS2
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@ -9,7 +9,6 @@ obj-y := entry.o traps.o irq.o debugport.o \
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process.o ptrace.o setup.o signal.o traps.o time.o \
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cache.o cacheflush.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_ETRAX_KGDB) += kgdb.o kgdb_asm.o
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obj-$(CONFIG_ETRAX_FAST_TIMER) += fasttimer.o
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obj-$(CONFIG_MODULES) += crisksyms.o
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@ -52,11 +52,6 @@ tstart:
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GIO_INIT
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#ifdef CONFIG_SMP
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secondary_cpu_entry: /* Entry point for secondary CPUs */
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di
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#endif
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;; Setup and enable the MMU. Use same configuration for both the data
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;; and the instruction MMU.
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;;
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@ -164,33 +159,6 @@ secondary_cpu_entry: /* Entry point for secondary CPUs */
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nop
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nop
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#ifdef CONFIG_SMP
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;; Read CPU ID
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move 0, $srs
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nop
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nop
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nop
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move $s12, $r0
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cmpq 0, $r0
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beq master_cpu
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nop
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slave_cpu:
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; Time to boot-up. Get stack location provided by master CPU.
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move.d smp_init_current_idle_thread, $r1
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move.d [$r1], $sp
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add.d 8192, $sp
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move.d ebp_start, $r0 ; Defined in linker-script.
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move $r0, $ebp
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jsr smp_callin
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nop
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master_cpu:
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/* Set up entry point for secondary CPUs. The boot ROM has set up
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* EBP at start of internal memory. The CPU will get there
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* later when we issue an IPI to them... */
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move.d MEM_INTMEM_START + IPI_INTR_VECT * 4, $r0
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move.d secondary_cpu_entry, $r1
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move.d $r1, [$r0]
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#endif
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; Check if starting from DRAM (network->RAM boot or unpacked
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; compressed kernel), or directly from flash.
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lapcq ., $r0
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@ -58,9 +58,6 @@ struct cris_irq_allocation irq_allocations[NR_REAL_IRQS] =
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static unsigned long irq_regs[NR_CPUS] =
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{
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regi_irq,
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#ifdef CONFIG_SMP
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regi_irq2,
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#endif
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};
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#if NR_REAL_IRQS > 32
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@ -63,11 +63,6 @@ int show_cpuinfo(struct seq_file *m, void *v)
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info = &cpinfo[ARRAY_SIZE(cpinfo) - 1];
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#ifdef CONFIG_SMP
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if (!cpu_online(cpu))
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return 0;
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#endif
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revision = rdvr();
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for (i = 0; i < ARRAY_SIZE(cpinfo); i++) {
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@ -1,358 +0,0 @@
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#include <linux/types.h>
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#include <asm/delay.h>
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#include <irq.h>
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#include <hwregs/intr_vect.h>
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#include <hwregs/intr_vect_defs.h>
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#include <asm/tlbflush.h>
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#include <asm/mmu_context.h>
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#include <hwregs/asm/mmu_defs_asm.h>
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#include <hwregs/supp_reg.h>
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#include <linux/atomic.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/timex.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/cpumask.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#define IPI_SCHEDULE 1
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#define IPI_CALL 2
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#define IPI_FLUSH_TLB 4
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#define IPI_BOOT 8
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#define FLUSH_ALL (void*)0xffffffff
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/* Vector of locks used for various atomic operations */
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spinlock_t cris_atomic_locks[] = {
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[0 ... LOCK_COUNT - 1] = __SPIN_LOCK_UNLOCKED(cris_atomic_locks)
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};
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/* CPU masks */
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cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
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EXPORT_SYMBOL(phys_cpu_present_map);
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/* Variables used during SMP boot */
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volatile int cpu_now_booting = 0;
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volatile struct thread_info *smp_init_current_idle_thread;
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/* Variables used during IPI */
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static DEFINE_SPINLOCK(call_lock);
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static DEFINE_SPINLOCK(tlbstate_lock);
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struct call_data_struct {
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void (*func) (void *info);
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void *info;
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int wait;
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};
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static struct call_data_struct * call_data;
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static struct mm_struct* flush_mm;
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static struct vm_area_struct* flush_vma;
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static unsigned long flush_addr;
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/* Mode registers */
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static unsigned long irq_regs[NR_CPUS] = {
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regi_irq,
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regi_irq2
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};
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static irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id);
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static int send_ipi(int vector, int wait, cpumask_t cpu_mask);
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static struct irqaction irq_ipi = {
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.handler = crisv32_ipi_interrupt,
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.flags = 0,
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.name = "ipi",
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};
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extern void cris_mmu_init(void);
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extern void cris_timer_init(void);
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/* SMP initialization */
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void __init smp_prepare_cpus(unsigned int max_cpus)
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{
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int i;
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/* From now on we can expect IPIs so set them up */
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setup_irq(IPI_INTR_VECT, &irq_ipi);
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/* Mark all possible CPUs as present */
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for (i = 0; i < max_cpus; i++)
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cpumask_set_cpu(i, &phys_cpu_present_map);
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}
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void smp_prepare_boot_cpu(void)
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{
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/* PGD pointer has moved after per_cpu initialization so
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* update the MMU.
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*/
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pgd_t **pgd;
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pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
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SUPP_BANK_SEL(1);
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SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
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SUPP_BANK_SEL(2);
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SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
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set_cpu_online(0, true);
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cpumask_set_cpu(0, &phys_cpu_present_map);
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set_cpu_possible(0, true);
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}
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void __init smp_cpus_done(unsigned int max_cpus)
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{
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}
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/* Bring one cpu online.*/
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static int __init
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smp_boot_one_cpu(int cpuid, struct task_struct idle)
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{
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unsigned timeout;
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cpumask_t cpu_mask;
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cpumask_clear(&cpu_mask);
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task_thread_info(idle)->cpu = cpuid;
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/* Information to the CPU that is about to boot */
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smp_init_current_idle_thread = task_thread_info(idle);
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cpu_now_booting = cpuid;
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/* Kick it */
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set_cpu_online(cpuid, true);
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cpumask_set_cpu(cpuid, &cpu_mask);
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send_ipi(IPI_BOOT, 0, cpu_mask);
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set_cpu_online(cpuid, false);
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/* Wait for CPU to come online */
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for (timeout = 0; timeout < 10000; timeout++) {
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if(cpu_online(cpuid)) {
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cpu_now_booting = 0;
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smp_init_current_idle_thread = NULL;
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return 0; /* CPU online */
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}
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udelay(100);
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barrier();
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}
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printk(KERN_CRIT "SMP: CPU:%d is stuck.\n", cpuid);
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return -1;
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}
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/* Secondary CPUs starts using C here. Here we need to setup CPU
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* specific stuff such as the local timer and the MMU. */
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void __init smp_callin(void)
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{
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int cpu = cpu_now_booting;
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reg_intr_vect_rw_mask vect_mask = {0};
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/* Initialise the idle task for this CPU */
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atomic_inc(&init_mm.mm_count);
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current->active_mm = &init_mm;
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/* Set up MMU */
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cris_mmu_init();
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__flush_tlb_all();
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/* Setup local timer. */
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cris_timer_init();
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/* Enable IRQ and idle */
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REG_WR(intr_vect, irq_regs[cpu], rw_mask, vect_mask);
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crisv32_unmask_irq(IPI_INTR_VECT);
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crisv32_unmask_irq(TIMER0_INTR_VECT);
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preempt_disable();
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notify_cpu_starting(cpu);
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local_irq_enable();
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set_cpu_online(cpu, true);
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cpu_startup_entry(CPUHP_ONLINE);
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}
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/* Stop execution on this CPU.*/
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void stop_this_cpu(void* dummy)
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{
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local_irq_disable();
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asm volatile("halt");
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}
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/* Other calls */
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void smp_send_stop(void)
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{
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smp_call_function(stop_this_cpu, NULL, 0);
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}
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int setup_profiling_timer(unsigned int multiplier)
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{
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return -EINVAL;
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}
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/* cache_decay_ticks is used by the scheduler to decide if a process
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* is "hot" on one CPU. A higher value means a higher penalty to move
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* a process to another CPU. Our cache is rather small so we report
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* 1 tick.
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*/
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unsigned long cache_decay_ticks = 1;
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int __cpu_up(unsigned int cpu, struct task_struct *tidle)
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{
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smp_boot_one_cpu(cpu, tidle);
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return cpu_online(cpu) ? 0 : -ENOSYS;
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}
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void smp_send_reschedule(int cpu)
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{
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cpumask_t cpu_mask;
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cpumask_clear(&cpu_mask);
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cpumask_set_cpu(cpu, &cpu_mask);
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send_ipi(IPI_SCHEDULE, 0, cpu_mask);
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}
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/* TLB flushing
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*
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* Flush needs to be done on the local CPU and on any other CPU that
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* may have the same mapping. The mm->cpu_vm_mask is used to keep track
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* of which CPUs that a specific process has been executed on.
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*/
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void flush_tlb_common(struct mm_struct* mm, struct vm_area_struct* vma, unsigned long addr)
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{
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unsigned long flags;
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cpumask_t cpu_mask;
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spin_lock_irqsave(&tlbstate_lock, flags);
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cpu_mask = (mm == FLUSH_ALL ? cpu_all_mask : *mm_cpumask(mm));
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cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
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flush_mm = mm;
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flush_vma = vma;
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flush_addr = addr;
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send_ipi(IPI_FLUSH_TLB, 1, cpu_mask);
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spin_unlock_irqrestore(&tlbstate_lock, flags);
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}
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void flush_tlb_all(void)
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{
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__flush_tlb_all();
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flush_tlb_common(FLUSH_ALL, FLUSH_ALL, 0);
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}
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void flush_tlb_mm(struct mm_struct *mm)
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{
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__flush_tlb_mm(mm);
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flush_tlb_common(mm, FLUSH_ALL, 0);
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/* No more mappings in other CPUs */
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cpumask_clear(mm_cpumask(mm));
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cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
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}
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void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long addr)
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{
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__flush_tlb_page(vma, addr);
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flush_tlb_common(vma->vm_mm, vma, addr);
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}
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/* Inter processor interrupts
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*
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* The IPIs are used for:
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* * Force a schedule on a CPU
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* * FLush TLB on other CPUs
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* * Call a function on other CPUs
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*/
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int send_ipi(int vector, int wait, cpumask_t cpu_mask)
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{
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int i = 0;
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reg_intr_vect_rw_ipi ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
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int ret = 0;
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/* Calculate CPUs to send to. */
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cpumask_and(&cpu_mask, &cpu_mask, cpu_online_mask);
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/* Send the IPI. */
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for_each_cpu(i, &cpu_mask)
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{
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ipi.vector |= vector;
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REG_WR(intr_vect, irq_regs[i], rw_ipi, ipi);
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}
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/* Wait for IPI to finish on other CPUS */
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if (wait) {
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for_each_cpu(i, &cpu_mask) {
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int j;
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for (j = 0 ; j < 1000; j++) {
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ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
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if (!ipi.vector)
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break;
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udelay(100);
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}
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/* Timeout? */
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if (ipi.vector) {
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printk("SMP call timeout from %d to %d\n", smp_processor_id(), i);
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ret = -ETIMEDOUT;
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dump_stack();
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}
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}
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}
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return ret;
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}
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/*
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* You must not call this function with disabled interrupts or from a
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* hardware interrupt handler or from a bottom half handler.
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*/
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int smp_call_function(void (*func)(void *info), void *info, int wait)
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{
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cpumask_t cpu_mask;
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struct call_data_struct data;
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int ret;
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cpumask_setall(&cpu_mask);
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cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
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WARN_ON(irqs_disabled());
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data.func = func;
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data.info = info;
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data.wait = wait;
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spin_lock(&call_lock);
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call_data = &data;
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ret = send_ipi(IPI_CALL, wait, cpu_mask);
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spin_unlock(&call_lock);
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return ret;
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}
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irqreturn_t crisv32_ipi_interrupt(int irq, void *dev_id)
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{
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void (*func) (void *info) = call_data->func;
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void *info = call_data->info;
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reg_intr_vect_rw_ipi ipi;
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ipi = REG_RD(intr_vect, irq_regs[smp_processor_id()], rw_ipi);
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if (ipi.vector & IPI_SCHEDULE) {
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scheduler_ipi();
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}
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if (ipi.vector & IPI_CALL) {
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func(info);
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}
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if (ipi.vector & IPI_FLUSH_TLB) {
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if (flush_mm == FLUSH_ALL)
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__flush_tlb_all();
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else if (flush_vma == FLUSH_ALL)
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__flush_tlb_mm(flush_mm);
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else
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__flush_tlb_page(flush_vma, flush_addr);
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}
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ipi.vector = 0;
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REG_WR(intr_vect, irq_regs[smp_processor_id()], rw_ipi, ipi);
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return IRQ_HANDLED;
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}
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@ -60,9 +60,6 @@ arch_initcall(etrax_init_cont_rotime);
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unsigned long timer_regs[NR_CPUS] =
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{
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regi_timer0,
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#ifdef CONFIG_SMP
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regi_timer2
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#endif
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};
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extern int set_rtc_mmss(unsigned long nowtime);
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@ -3,5 +3,5 @@
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#
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lib-y = checksum.o checksumcopy.o string.o usercopy.o memset.o \
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csumcpfruser.o spinlock.o delay.o strcmp.o
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csumcpfruser.o delay.o strcmp.o
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@ -1,40 +0,0 @@
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;; Core of the spinlock implementation
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;;
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;; Copyright (C) 2004 Axis Communications AB.
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;;
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;; Author: Mikael Starvik
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.global cris_spin_lock
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.type cris_spin_lock,@function
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.global cris_spin_trylock
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.type cris_spin_trylock,@function
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.text
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||||
|
||||
cris_spin_lock:
|
||||
clearf p
|
||||
1: test.b [$r10]
|
||||
beq 1b
|
||||
clearf p
|
||||
ax
|
||||
clear.b [$r10]
|
||||
bcs 1b
|
||||
clearf p
|
||||
ret
|
||||
nop
|
||||
|
||||
.size cris_spin_lock, . - cris_spin_lock
|
||||
|
||||
cris_spin_trylock:
|
||||
clearf p
|
||||
1: move.b [$r10], $r11
|
||||
ax
|
||||
clear.b [$r10]
|
||||
bcs 1b
|
||||
clearf p
|
||||
ret
|
||||
movu.b $r11,$r10
|
||||
|
||||
.size cris_spin_trylock, . - cris_spin_trylock
|
||||
|
||||
|
|
@ -40,17 +40,6 @@ void __init cris_mmu_init(void)
|
|||
*/
|
||||
per_cpu(current_pgd, smp_processor_id()) = init_mm.pgd;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
{
|
||||
pgd_t **pgd;
|
||||
pgd = (pgd_t**)&per_cpu(current_pgd, smp_processor_id());
|
||||
SUPP_BANK_SEL(1);
|
||||
SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
|
||||
SUPP_BANK_SEL(2);
|
||||
SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Initialise the TLB. Function found in tlb.c. */
|
||||
tlb_init();
|
||||
|
||||
|
|
|
|||
|
|
@ -115,11 +115,7 @@
|
|||
move.d $r0, [$r1] ; last_refill_cause = rw_mm_cause
|
||||
|
||||
3: ; Probably not in a loop, continue normal processing
|
||||
#ifdef CONFIG_SMP
|
||||
move $s7, $acr ; PGD
|
||||
#else
|
||||
move.d current_pgd, $acr ; PGD
|
||||
#endif
|
||||
; Look up PMD in PGD
|
||||
lsrq 24, $r0 ; Get PMD index into PGD (bit 24-31)
|
||||
move.d [$acr], $acr ; PGD for the current process
|
||||
|
|
|
|||
|
|
@ -1,36 +1,8 @@
|
|||
#ifndef __ASM_CRIS_ARCH_ATOMIC__
|
||||
#define __ASM_CRIS_ARCH_ATOMIC__
|
||||
|
||||
#include <linux/spinlock_types.h>
|
||||
|
||||
extern void cris_spin_unlock(void *l, int val);
|
||||
extern void cris_spin_lock(void *l);
|
||||
extern int cris_spin_trylock(void* l);
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
#define cris_atomic_save(addr, flags) local_irq_save(flags);
|
||||
#define cris_atomic_restore(addr, flags) local_irq_restore(flags);
|
||||
#else
|
||||
|
||||
extern spinlock_t cris_atomic_locks[];
|
||||
#define LOCK_COUNT 128
|
||||
#define HASH_ADDR(a) (((int)a) & 127)
|
||||
|
||||
#define cris_atomic_save(addr, flags) \
|
||||
local_irq_save(flags); \
|
||||
cris_spin_lock((void *)&cris_atomic_locks[HASH_ADDR(addr)].raw_lock.slock);
|
||||
|
||||
#define cris_atomic_restore(addr, flags) \
|
||||
{ \
|
||||
spinlock_t *lock = (void*)&cris_atomic_locks[HASH_ADDR(addr)]; \
|
||||
__asm__ volatile ("move.d %1,%0" \
|
||||
: "=m" (lock->raw_lock.slock) \
|
||||
: "r" (1) \
|
||||
: "memory"); \
|
||||
local_irq_restore(flags); \
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1,131 +0,0 @@
|
|||
#ifndef __ASM_ARCH_SPINLOCK_H
|
||||
#define __ASM_ARCH_SPINLOCK_H
|
||||
|
||||
#include <linux/spinlock_types.h>
|
||||
|
||||
#define RW_LOCK_BIAS 0x01000000
|
||||
|
||||
extern void cris_spin_unlock(void *l, int val);
|
||||
extern void cris_spin_lock(void *l);
|
||||
extern int cris_spin_trylock(void *l);
|
||||
|
||||
static inline int arch_spin_is_locked(arch_spinlock_t *x)
|
||||
{
|
||||
return *(volatile signed char *)(&(x)->slock) <= 0;
|
||||
}
|
||||
|
||||
static inline void arch_spin_unlock(arch_spinlock_t *lock)
|
||||
{
|
||||
__asm__ volatile ("move.d %1,%0" \
|
||||
: "=m" (lock->slock) \
|
||||
: "r" (1) \
|
||||
: "memory");
|
||||
}
|
||||
|
||||
static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
|
||||
{
|
||||
while (arch_spin_is_locked(lock))
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
static inline int arch_spin_trylock(arch_spinlock_t *lock)
|
||||
{
|
||||
return cris_spin_trylock((void *)&lock->slock);
|
||||
}
|
||||
|
||||
static inline void arch_spin_lock(arch_spinlock_t *lock)
|
||||
{
|
||||
cris_spin_lock((void *)&lock->slock);
|
||||
}
|
||||
|
||||
static inline void
|
||||
arch_spin_lock_flags(arch_spinlock_t *lock, unsigned long flags)
|
||||
{
|
||||
arch_spin_lock(lock);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read-write spinlocks, allowing multiple readers
|
||||
* but only one writer.
|
||||
*
|
||||
* NOTE! it is quite common to have readers in interrupts
|
||||
* but no interrupt writers. For those circumstances we
|
||||
* can "mix" irq-safe locks - any writer needs to get a
|
||||
* irq-safe write-lock, but readers can get non-irqsafe
|
||||
* read-locks.
|
||||
*
|
||||
*/
|
||||
|
||||
static inline int arch_read_can_lock(arch_rwlock_t *x)
|
||||
{
|
||||
return (int)(x)->lock > 0;
|
||||
}
|
||||
|
||||
static inline int arch_write_can_lock(arch_rwlock_t *x)
|
||||
{
|
||||
return (x)->lock == RW_LOCK_BIAS;
|
||||
}
|
||||
|
||||
static inline void arch_read_lock(arch_rwlock_t *rw)
|
||||
{
|
||||
arch_spin_lock(&rw->slock);
|
||||
while (rw->lock == 0);
|
||||
rw->lock--;
|
||||
arch_spin_unlock(&rw->slock);
|
||||
}
|
||||
|
||||
static inline void arch_write_lock(arch_rwlock_t *rw)
|
||||
{
|
||||
arch_spin_lock(&rw->slock);
|
||||
while (rw->lock != RW_LOCK_BIAS);
|
||||
rw->lock = 0;
|
||||
arch_spin_unlock(&rw->slock);
|
||||
}
|
||||
|
||||
static inline void arch_read_unlock(arch_rwlock_t *rw)
|
||||
{
|
||||
arch_spin_lock(&rw->slock);
|
||||
rw->lock++;
|
||||
arch_spin_unlock(&rw->slock);
|
||||
}
|
||||
|
||||
static inline void arch_write_unlock(arch_rwlock_t *rw)
|
||||
{
|
||||
arch_spin_lock(&rw->slock);
|
||||
while (rw->lock != RW_LOCK_BIAS);
|
||||
rw->lock = RW_LOCK_BIAS;
|
||||
arch_spin_unlock(&rw->slock);
|
||||
}
|
||||
|
||||
static inline int arch_read_trylock(arch_rwlock_t *rw)
|
||||
{
|
||||
int ret = 0;
|
||||
arch_spin_lock(&rw->slock);
|
||||
if (rw->lock != 0) {
|
||||
rw->lock--;
|
||||
ret = 1;
|
||||
}
|
||||
arch_spin_unlock(&rw->slock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline int arch_write_trylock(arch_rwlock_t *rw)
|
||||
{
|
||||
int ret = 0;
|
||||
arch_spin_lock(&rw->slock);
|
||||
if (rw->lock == RW_LOCK_BIAS) {
|
||||
rw->lock = 0;
|
||||
ret = 1;
|
||||
}
|
||||
arch_spin_unlock(&rw->slock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
#define _raw_read_lock_flags(lock, flags) _raw_read_lock(lock)
|
||||
#define _raw_write_lock_flags(lock, flags) _raw_write_lock(lock)
|
||||
|
||||
#define arch_spin_relax(lock) cpu_relax()
|
||||
#define arch_read_relax(lock) cpu_relax()
|
||||
#define arch_write_relax(lock) cpu_relax()
|
||||
|
||||
#endif /* __ASM_ARCH_SPINLOCK_H */
|
||||
|
|
@ -46,8 +46,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
|
|||
(unsigned long)(n), sizeof(*(ptr))))
|
||||
#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
#include <asm-generic/cmpxchg.h>
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CRIS_CMPXCHG__ */
|
||||
|
|
|
|||
|
|
@ -1,10 +0,0 @@
|
|||
#ifndef __ASM_SMP_H
|
||||
#define __ASM_SMP_H
|
||||
|
||||
#include <linux/cpumask.h>
|
||||
|
||||
extern cpumask_t phys_cpu_present_map;
|
||||
|
||||
#define raw_smp_processor_id() (current_thread_info()->cpu)
|
||||
|
||||
#endif
|
||||
|
|
@ -1 +0,0 @@
|
|||
#include <arch/spinlock.h>
|
||||
|
|
@ -22,16 +22,9 @@ extern void __flush_tlb_mm(struct mm_struct *mm);
|
|||
extern void __flush_tlb_page(struct vm_area_struct *vma,
|
||||
unsigned long addr);
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
extern void flush_tlb_all(void);
|
||||
extern void flush_tlb_mm(struct mm_struct *mm);
|
||||
extern void flush_tlb_page(struct vm_area_struct *vma,
|
||||
unsigned long addr);
|
||||
#else
|
||||
#define flush_tlb_all __flush_tlb_all
|
||||
#define flush_tlb_mm __flush_tlb_mm
|
||||
#define flush_tlb_page __flush_tlb_page
|
||||
#endif
|
||||
|
||||
static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end)
|
||||
{
|
||||
|
|
|
|||
Loading…
Reference in New Issue