[BNX2]: Add init. code to handle RX pages.
Add new fields to keep track of the pages and the page rings. Add functions to allocate and free pages. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
110d0ef990
commit
47bf4246a3
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@ -483,6 +483,16 @@ bnx2_free_mem(struct bnx2 *bp)
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}
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}
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vfree(bp->rx_buf_ring);
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vfree(bp->rx_buf_ring);
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bp->rx_buf_ring = NULL;
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bp->rx_buf_ring = NULL;
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for (i = 0; i < bp->rx_max_pg_ring; i++) {
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if (bp->rx_pg_desc_ring[i])
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pci_free_consistent(bp->pdev, RXBD_RING_SIZE,
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bp->rx_pg_desc_ring[i],
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bp->rx_pg_desc_mapping[i]);
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bp->rx_pg_desc_ring[i] = NULL;
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}
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if (bp->rx_pg_ring)
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vfree(bp->rx_pg_ring);
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bp->rx_pg_ring = NULL;
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}
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}
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static int
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static int
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@ -514,6 +524,25 @@ bnx2_alloc_mem(struct bnx2 *bp)
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}
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}
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if (bp->rx_pg_ring_size) {
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bp->rx_pg_ring = vmalloc(SW_RXPG_RING_SIZE *
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bp->rx_max_pg_ring);
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if (bp->rx_pg_ring == NULL)
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goto alloc_mem_err;
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memset(bp->rx_pg_ring, 0, SW_RXPG_RING_SIZE *
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bp->rx_max_pg_ring);
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}
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for (i = 0; i < bp->rx_max_pg_ring; i++) {
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bp->rx_pg_desc_ring[i] =
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pci_alloc_consistent(bp->pdev, RXBD_RING_SIZE,
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&bp->rx_pg_desc_mapping[i]);
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if (bp->rx_pg_desc_ring[i] == NULL)
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goto alloc_mem_err;
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}
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/* Combine status and statistics blocks into one allocation. */
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/* Combine status and statistics blocks into one allocation. */
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status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
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status_blk_size = L1_CACHE_ALIGN(sizeof(struct status_block));
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bp->status_stats_size = status_blk_size +
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bp->status_stats_size = status_blk_size +
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@ -2194,6 +2223,42 @@ bnx2_set_mac_addr(struct bnx2 *bp)
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REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
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REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
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}
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}
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static inline int
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bnx2_alloc_rx_page(struct bnx2 *bp, u16 index)
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{
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dma_addr_t mapping;
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struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
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struct rx_bd *rxbd =
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&bp->rx_pg_desc_ring[RX_RING(index)][RX_IDX(index)];
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struct page *page = alloc_page(GFP_ATOMIC);
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if (!page)
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return -ENOMEM;
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mapping = pci_map_page(bp->pdev, page, 0, PAGE_SIZE,
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PCI_DMA_FROMDEVICE);
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rx_pg->page = page;
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pci_unmap_addr_set(rx_pg, mapping, mapping);
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rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
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rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
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return 0;
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}
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static void
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bnx2_free_rx_page(struct bnx2 *bp, u16 index)
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{
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struct sw_pg *rx_pg = &bp->rx_pg_ring[index];
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struct page *page = rx_pg->page;
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if (!page)
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return;
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pci_unmap_page(bp->pdev, pci_unmap_addr(rx_pg, mapping), PAGE_SIZE,
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PCI_DMA_FROMDEVICE);
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__free_page(page);
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rx_pg->page = NULL;
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}
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static inline int
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static inline int
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bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
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bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
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{
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{
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@ -4213,11 +4278,31 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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bp->rx_prod = 0;
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bp->rx_prod = 0;
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bp->rx_cons = 0;
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bp->rx_cons = 0;
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bp->rx_prod_bseq = 0;
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bp->rx_prod_bseq = 0;
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bp->rx_pg_prod = 0;
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bp->rx_pg_cons = 0;
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bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
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bnx2_init_rxbd_rings(bp->rx_desc_ring, bp->rx_desc_mapping,
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bp->rx_buf_use_size, bp->rx_max_ring);
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bp->rx_buf_use_size, bp->rx_max_ring);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, 0);
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if (bp->rx_pg_ring_size) {
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bnx2_init_rxbd_rings(bp->rx_pg_desc_ring,
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bp->rx_pg_desc_mapping,
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PAGE_SIZE, bp->rx_max_pg_ring);
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val = (bp->rx_buf_use_size << 16) | PAGE_SIZE;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_PG_BUF_SIZE, val);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_RBDC_KEY,
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BNX2_L2CTX_RBDC_JUMBO_KEY);
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val = (u64) bp->rx_pg_desc_mapping[0] >> 32;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_HI, val);
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val = (u64) bp->rx_pg_desc_mapping[0] & 0xffffffff;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_PG_BDHADDR_LO, val);
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if (CHIP_NUM(bp) == CHIP_NUM_5709)
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REG_WR(bp, BNX2_MQ_MAP_L2_3, BNX2_MQ_MAP_L2_3_DEFAULT);
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}
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val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
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val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
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val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
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val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
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@ -4230,6 +4315,15 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
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val = (u64) bp->rx_desc_mapping[0] & 0xffffffff;
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
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CTX_WR(bp, rx_cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
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ring_prod = prod = bp->rx_pg_prod;
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for (i = 0; i < bp->rx_pg_ring_size; i++) {
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if (bnx2_alloc_rx_page(bp, ring_prod) < 0)
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break;
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prod = NEXT_RX_BD(prod);
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ring_prod = RX_PG_RING_IDX(prod);
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}
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bp->rx_pg_prod = prod;
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ring_prod = prod = bp->rx_prod;
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ring_prod = prod = bp->rx_prod;
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for (i = 0; i < bp->rx_ring_size; i++) {
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for (i = 0; i < bp->rx_ring_size; i++) {
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if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
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if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
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@ -4240,6 +4334,7 @@ bnx2_init_rx_ring(struct bnx2 *bp)
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}
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}
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bp->rx_prod = prod;
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bp->rx_prod = prod;
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REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_PG_BDIDX, bp->rx_pg_prod);
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REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
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REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
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REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
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REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
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@ -4273,6 +4368,9 @@ bnx2_set_rx_ring_size(struct bnx2 *bp, u32 size)
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rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
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rx_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
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bp->rx_copy_thresh = RX_COPY_THRESH;
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bp->rx_copy_thresh = RX_COPY_THRESH;
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bp->rx_pg_ring_size = 0;
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bp->rx_max_pg_ring = 0;
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bp->rx_max_pg_ring_idx = 0;
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bp->rx_buf_use_size = rx_size;
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bp->rx_buf_use_size = rx_size;
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/* hw alignment */
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/* hw alignment */
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@ -4341,6 +4439,8 @@ bnx2_free_rx_skbs(struct bnx2 *bp)
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dev_kfree_skb(skb);
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dev_kfree_skb(skb);
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}
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}
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for (i = 0; i < bp->rx_max_pg_ring_idx; i++)
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bnx2_free_rx_page(bp, i);
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}
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}
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static void
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static void
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@ -5813,11 +5913,11 @@ bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
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ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
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ering->rx_max_pending = MAX_TOTAL_RX_DESC_CNT;
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ering->rx_mini_max_pending = 0;
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ering->rx_mini_max_pending = 0;
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ering->rx_jumbo_max_pending = 0;
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ering->rx_jumbo_max_pending = MAX_TOTAL_RX_PG_DESC_CNT;
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ering->rx_pending = bp->rx_ring_size;
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ering->rx_pending = bp->rx_ring_size;
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ering->rx_mini_pending = 0;
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ering->rx_mini_pending = 0;
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ering->rx_jumbo_pending = 0;
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ering->rx_jumbo_pending = bp->rx_pg_ring_size;
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ering->tx_max_pending = MAX_TX_DESC_CNT;
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ering->tx_max_pending = MAX_TX_DESC_CNT;
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ering->tx_pending = bp->tx_ring_size;
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ering->tx_pending = bp->tx_ring_size;
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@ -335,6 +335,7 @@ struct l2_fhdr {
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#define BNX2_L2CTX_HOST_PG_BDIDX 0x00000044
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#define BNX2_L2CTX_HOST_PG_BDIDX 0x00000044
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#define BNX2_L2CTX_PG_BUF_SIZE 0x00000048
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#define BNX2_L2CTX_PG_BUF_SIZE 0x00000048
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#define BNX2_L2CTX_RBDC_KEY 0x0000004c
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#define BNX2_L2CTX_RBDC_KEY 0x0000004c
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#define BNX2_L2CTX_RBDC_JUMBO_KEY 0x3ffe
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#define BNX2_L2CTX_NX_PG_BDHADDR_HI 0x00000050
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#define BNX2_L2CTX_NX_PG_BDHADDR_HI 0x00000050
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#define BNX2_L2CTX_NX_PG_BDHADDR_LO 0x00000054
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#define BNX2_L2CTX_NX_PG_BDHADDR_LO 0x00000054
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@ -4450,6 +4451,14 @@ struct l2_fhdr {
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#define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
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#define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
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#define BNX2_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0)
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#define BNX2_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0)
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#define BNX2_MQ_MAP_L2_3 0x00003d2c
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#define BNX2_MQ_MAP_L2_3_MQ_OFFSET (0xffL<<0)
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#define BNX2_MQ_MAP_L2_3_SZ (0x3L<<8)
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#define BNX2_MQ_MAP_L2_3_CTX_OFFSET (0x2ffL<<10)
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#define BNX2_MQ_MAP_L2_3_BIN_OFFSET (0x7L<<23)
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#define BNX2_MQ_MAP_L2_3_ARM (0x3L<<26)
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#define BNX2_MQ_MAP_L2_3_ENA (0x1L<<31)
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#define BNX2_MQ_MAP_L2_3_DEFAULT 0x82004646
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/*
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/*
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* tsch_reg definition
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* tsch_reg definition
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@ -6360,9 +6369,11 @@ struct l2_fhdr {
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#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
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#define MAX_TX_DESC_CNT (TX_DESC_CNT - 1)
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#define MAX_RX_RINGS 4
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#define MAX_RX_RINGS 4
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#define MAX_RX_PG_RINGS 16
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#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
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#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct rx_bd))
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#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
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#define MAX_RX_DESC_CNT (RX_DESC_CNT - 1)
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#define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
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#define MAX_TOTAL_RX_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_RINGS)
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#define MAX_TOTAL_RX_PG_DESC_CNT (MAX_RX_DESC_CNT * MAX_RX_PG_RINGS)
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#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
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#define NEXT_TX_BD(x) (((x) & (MAX_TX_DESC_CNT - 1)) == \
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(MAX_TX_DESC_CNT - 1)) ? \
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(MAX_TX_DESC_CNT - 1)) ? \
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@ -6375,6 +6386,7 @@ struct l2_fhdr {
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(x) + 2 : (x) + 1
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(x) + 2 : (x) + 1
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#define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
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#define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
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#define RX_PG_RING_IDX(x) ((x) & bp->rx_max_pg_ring_idx)
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#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> (BCM_PAGE_BITS - 4))
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#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> (BCM_PAGE_BITS - 4))
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#define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
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#define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
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@ -6413,7 +6425,13 @@ struct sw_bd {
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DECLARE_PCI_UNMAP_ADDR(mapping)
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DECLARE_PCI_UNMAP_ADDR(mapping)
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};
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};
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struct sw_pg {
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struct page *page;
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DECLARE_PCI_UNMAP_ADDR(mapping)
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};
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#define SW_RXBD_RING_SIZE (sizeof(struct sw_bd) * RX_DESC_CNT)
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#define SW_RXBD_RING_SIZE (sizeof(struct sw_bd) * RX_DESC_CNT)
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#define SW_RXPG_RING_SIZE (sizeof(struct sw_pg) * RX_DESC_CNT)
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#define RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
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#define RXBD_RING_SIZE (sizeof(struct rx_bd) * RX_DESC_CNT)
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#define SW_TXBD_RING_SIZE (sizeof(struct sw_bd) * TX_DESC_CNT)
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#define SW_TXBD_RING_SIZE (sizeof(struct sw_bd) * TX_DESC_CNT)
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#define TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
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#define TXBD_RING_SIZE (sizeof(struct tx_bd) * TX_DESC_CNT)
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@ -6520,15 +6538,21 @@ struct bnx2 {
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u32 rx_buf_size; /* with alignment */
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u32 rx_buf_size; /* with alignment */
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u32 rx_copy_thresh;
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u32 rx_copy_thresh;
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u32 rx_max_ring_idx;
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u32 rx_max_ring_idx;
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u32 rx_max_pg_ring_idx;
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u32 rx_prod_bseq;
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u32 rx_prod_bseq;
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u16 rx_prod;
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u16 rx_prod;
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u16 rx_cons;
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u16 rx_cons;
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u16 rx_pg_prod;
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u16 rx_pg_cons;
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u32 rx_csum;
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u32 rx_csum;
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struct sw_bd *rx_buf_ring;
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struct sw_bd *rx_buf_ring;
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struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
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struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
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struct sw_pg *rx_pg_ring;
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struct rx_bd *rx_pg_desc_ring[MAX_RX_PG_RINGS];
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/* TX constants */
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/* TX constants */
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struct tx_bd *tx_desc_ring;
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struct tx_bd *tx_desc_ring;
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@ -6616,6 +6640,10 @@ struct bnx2 {
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int rx_ring_size;
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int rx_ring_size;
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dma_addr_t rx_desc_mapping[MAX_RX_RINGS];
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dma_addr_t rx_desc_mapping[MAX_RX_RINGS];
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int rx_max_pg_ring;
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int rx_pg_ring_size;
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dma_addr_t rx_pg_desc_mapping[MAX_RX_PG_RINGS];
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u16 tx_quick_cons_trip;
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u16 tx_quick_cons_trip;
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u16 tx_quick_cons_trip_int;
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u16 tx_quick_cons_trip_int;
|
||||||
u16 rx_quick_cons_trip;
|
u16 rx_quick_cons_trip;
|
||||||
|
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Loading…
Reference in New Issue