staging: comedi: adv_pci1710: convert driver to use the comedi_8254 module
This driver uses an 8254 timer to generate the pacer clock used for analog input data acquisition. It also provides a comedi_subdevice to allow the user to use channel 0 of the 8254 timer. Currently the subdevice support does not work correctly due to and (*insn_config) that does not follow the comedi API. Convert it to use the comedi_8254 module to provide support for the 8254 timer and proper support for the subdevice. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
a90feb7fd0
commit
48a4f22266
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@ -739,6 +739,7 @@ config COMEDI_ADL_PCI9118
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config COMEDI_ADV_PCI1710
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tristate "Advantech PCI-171x, PCI-1720 and PCI-1731 support"
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select COMEDI_8254
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---help---
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Enable support for Advantech PCI-1710, PCI-1710HG, PCI-1711,
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PCI-1713, PCI-1720 and PCI-1731
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@ -48,7 +48,7 @@ Configuration options:
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#include "../comedidev.h"
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#include "comedi_fc.h"
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#include "8253.h"
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#include "comedi_8254.h"
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#include "amcc_s5933.h"
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#define PCI171x_AD_DATA 0 /* R: A/D data */
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@ -67,11 +67,6 @@ Configuration options:
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#define PCI171X_TIMER_BASE 0x18
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#define PCI171x_CNT0 24 /* R/W: 8254 counter 0 */
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#define PCI171x_CNT1 26 /* R/W: 8254 counter 1 */
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#define PCI171x_CNT2 28 /* R/W: 8254 counter 2 */
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#define PCI171x_CNTCTRL 30 /* W: 8254 counter control */
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/* upper bits from status register (PCI171x_STATUS) (lower is same with control
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* reg) */
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#define Status_FE 0x0100 /* 1=FIFO is empty */
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@ -87,16 +82,6 @@ Configuration options:
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#define Control_EXT 0x0004 /* 1=external trigger source */
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#define Control_PACER 0x0002 /* 1=enable internal 8254 trigger source */
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#define Control_SW 0x0001 /* 1=enable software trigger source */
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/* bits from counter control register (PCI171x_CNTCTRL) */
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#define Counter_BCD 0x0001 /* 0 = binary counter, 1 = BCD counter */
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#define Counter_M0 0x0002 /* M0-M2 select modes 0-5 */
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#define Counter_M1 0x0004 /* 000 = mode 0, 010 = mode 2 ... */
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#define Counter_M2 0x0008
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#define Counter_RW0 0x0010 /* RW0/RW1 select read/write mode */
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#define Counter_RW1 0x0020
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#define Counter_SC0 0x0040 /* Select Counter. Only 00 or 11 may */
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#define Counter_SC1 0x0080 /* be used, 00 for CNT0,
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* 11 for read-back command */
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#define PCI1720_DA0 0 /* W: D/A register 0 */
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#define PCI1720_DA1 2 /* W: D/A register 1 */
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@ -265,15 +250,9 @@ struct pci1710_private {
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unsigned char ai_et;
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unsigned int ai_et_CntrlReg;
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unsigned int ai_et_MuxVal;
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unsigned int next_divisor1;
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unsigned int next_divisor2;
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unsigned int divisor1;
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unsigned int divisor2;
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unsigned int act_chanlist[32]; /* list of scanned channel */
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unsigned char saved_seglen; /* len of the non-repeating chanlist */
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unsigned char da_ranges; /* copy of D/A outpit range register */
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unsigned int cnt0_write_wait; /* after a write, wait for update of the
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* internal state */
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};
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static int pci171x_ai_check_chanlist(struct comedi_device *dev,
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@ -509,105 +488,6 @@ static int pci171x_do_insn_bits(struct comedi_device *dev,
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return insn->n;
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}
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static void pci171x_start_pacer(struct comedi_device *dev,
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bool load_counters)
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{
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struct pci1710_private *devpriv = dev->private;
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unsigned long timer_base = dev->iobase + PCI171X_TIMER_BASE;
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i8254_set_mode(timer_base, 1, 2, I8254_MODE2 | I8254_BINARY);
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i8254_set_mode(timer_base, 1, 1, I8254_MODE2 | I8254_BINARY);
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if (load_counters) {
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i8254_write(timer_base, 1, 2, devpriv->divisor2);
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i8254_write(timer_base, 1, 1, devpriv->divisor1);
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}
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}
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static int pci171x_counter_insn_read(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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unsigned int msb, lsb, ccntrl;
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int i;
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ccntrl = 0xD2; /* count only */
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for (i = 0; i < insn->n; i++) {
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outw(ccntrl, dev->iobase + PCI171x_CNTCTRL);
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lsb = inw(dev->iobase + PCI171x_CNT0) & 0xFF;
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msb = inw(dev->iobase + PCI171x_CNT0) & 0xFF;
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data[0] = lsb | (msb << 8);
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}
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return insn->n;
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}
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static int pci171x_counter_insn_write(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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struct pci1710_private *devpriv = dev->private;
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uint msb, lsb, ccntrl, status;
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lsb = data[0] & 0x00FF;
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msb = (data[0] & 0xFF00) >> 8;
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/* write lsb, then msb */
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outw(lsb, dev->iobase + PCI171x_CNT0);
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outw(msb, dev->iobase + PCI171x_CNT0);
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if (devpriv->cnt0_write_wait) {
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/* wait for the new count to be loaded */
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ccntrl = 0xE2;
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do {
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outw(ccntrl, dev->iobase + PCI171x_CNTCTRL);
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status = inw(dev->iobase + PCI171x_CNT0) & 0xFF;
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} while (status & 0x40);
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}
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return insn->n;
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}
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static int pci171x_counter_insn_config(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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#ifdef unused
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/* This doesn't work like a normal Comedi counter config */
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struct pci1710_private *devpriv = dev->private;
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uint ccntrl = 0;
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devpriv->cnt0_write_wait = data[0] & 0x20;
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/* internal or external clock? */
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if (!(data[0] & 0x10)) { /* internal */
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devpriv->CntrlReg &= ~Control_CNT0;
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} else {
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devpriv->CntrlReg |= Control_CNT0;
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}
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outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
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if (data[0] & 0x01)
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ccntrl |= Counter_M0;
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if (data[0] & 0x02)
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ccntrl |= Counter_M1;
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if (data[0] & 0x04)
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ccntrl |= Counter_M2;
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if (data[0] & 0x08)
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ccntrl |= Counter_BCD;
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ccntrl |= Counter_RW0; /* set read/write mode */
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ccntrl |= Counter_RW1;
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outw(ccntrl, dev->iobase + PCI171x_CNTCTRL);
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#endif
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return 1;
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}
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static int pci1720_ao_insn_write(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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@ -647,7 +527,7 @@ static int pci171x_ai_cancel(struct comedi_device *dev,
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devpriv->CntrlReg |= Control_SW;
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/* reset any operations */
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outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
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pci171x_start_pacer(dev, false);
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comedi_8254_pacer_enable(dev->pacer, 1, 2, false);
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outb(0, dev->iobase + PCI171x_CLRFIFO);
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outb(0, dev->iobase + PCI171x_CLRINT);
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@ -768,7 +648,7 @@ static irqreturn_t interrupt_service_pci1710(int irq, void *d)
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outb(0, dev->iobase + PCI171x_CLRINT);
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outw(devpriv->ai_et_MuxVal, dev->iobase + PCI171x_MUX);
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outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
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pci171x_start_pacer(dev, true);
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comedi_8254_pacer_enable(dev->pacer, 1, 2, true);
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return IRQ_HANDLED;
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}
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@ -787,8 +667,6 @@ static int pci171x_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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struct pci1710_private *devpriv = dev->private;
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struct comedi_cmd *cmd = &s->async->cmd;
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pci171x_start_pacer(dev, false);
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pci171x_ai_setup_chanlist(dev, s, cmd->chanlist, cmd->chanlist_len,
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devpriv->saved_seglen);
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@ -799,10 +677,9 @@ static int pci171x_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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if ((cmd->flags & CMDF_WAKE_EOS) == 0)
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devpriv->CntrlReg |= Control_ONEFH;
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devpriv->divisor1 = devpriv->next_divisor1;
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devpriv->divisor2 = devpriv->next_divisor2;
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if (cmd->convert_src == TRIG_TIMER) {
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comedi_8254_update_divisors(dev->pacer);
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devpriv->CntrlReg |= Control_PACER | Control_IRQEN;
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if (cmd->start_src == TRIG_EXT) {
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devpriv->ai_et_CntrlReg = devpriv->CntrlReg;
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@ -816,7 +693,7 @@ static int pci171x_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
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if (cmd->start_src == TRIG_NOW)
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pci171x_start_pacer(dev, true);
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comedi_8254_pacer_enable(dev->pacer, 1, 2, true);
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} else { /* TRIG_EXT */
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devpriv->CntrlReg |= Control_EXT | Control_IRQEN;
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outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
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@ -829,9 +706,7 @@ static int pci171x_ai_cmdtest(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_cmd *cmd)
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{
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struct pci1710_private *devpriv = dev->private;
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int err = 0;
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unsigned int arg;
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/* Step 1 : check if triggers are trivially valid */
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@ -878,11 +753,9 @@ static int pci171x_ai_cmdtest(struct comedi_device *dev,
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/* step 4: fix up any arguments */
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if (cmd->convert_src == TRIG_TIMER) {
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arg = cmd->convert_arg;
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i8253_cascade_ns_to_timer(I8254_OSC_BASE_10MHZ,
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&devpriv->next_divisor1,
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&devpriv->next_divisor2,
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&arg, cmd->flags);
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unsigned int arg = cmd->convert_arg;
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comedi_8254_cascade_ns_to_timer(dev->pacer, &arg, cmd->flags);
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err |= cfc_check_trigger_arg_is(&cmd->convert_arg, arg);
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}
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@ -899,19 +772,54 @@ static int pci171x_ai_cmdtest(struct comedi_device *dev,
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return 0;
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}
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static int pci171x_insn_counter_config(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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struct pci1710_private *devpriv = dev->private;
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switch (data[0]) {
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case INSN_CONFIG_SET_CLOCK_SRC:
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switch (data[1]) {
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case 0: /* internal */
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devpriv->ai_et_CntrlReg &= ~Control_CNT0;
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break;
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case 1: /* external */
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devpriv->ai_et_CntrlReg |= Control_CNT0;
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break;
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default:
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return -EINVAL;
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}
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outw(devpriv->ai_et_CntrlReg, dev->iobase + PCI171x_CONTROL);
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break;
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case INSN_CONFIG_GET_CLOCK_SRC:
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if (devpriv->ai_et_CntrlReg & Control_CNT0) {
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data[1] = 1;
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data[2] = 0;
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} else {
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data[1] = 0;
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data[2] = I8254_OSC_BASE_10MHZ;
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}
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break;
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default:
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return -EINVAL;
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}
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return insn->n;
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}
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static int pci171x_reset(struct comedi_device *dev)
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{
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const struct boardtype *board = dev->board_ptr;
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struct pci1710_private *devpriv = dev->private;
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outw(0x30, dev->iobase + PCI171x_CNTCTRL);
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/* Software trigger, CNT0=external */
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devpriv->CntrlReg = Control_SW | Control_CNT0;
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/* reset any operations */
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outw(devpriv->CntrlReg, dev->iobase + PCI171x_CONTROL);
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outb(0, dev->iobase + PCI171x_CLRFIFO); /* clear FIFO */
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outb(0, dev->iobase + PCI171x_CLRINT); /* clear INT request */
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pci171x_start_pacer(dev, false);
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devpriv->da_ranges = 0;
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if (board->has_ao) {
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/* set DACs to 0..5V */
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@ -978,6 +886,11 @@ static int pci1710_auto_attach(struct comedi_device *dev,
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return ret;
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dev->iobase = pci_resource_start(pcidev, 2);
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dev->pacer = comedi_8254_init(dev->iobase + PCI171X_TIMER_BASE,
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I8254_OSC_BASE_10MHZ, I8254_IO16, 0);
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if (!dev->pacer)
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return -ENOMEM;
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n_subdevices = 0;
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if (board->n_aichan)
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n_subdevices++;
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@ -1074,16 +987,17 @@ static int pci1710_auto_attach(struct comedi_device *dev,
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subdev++;
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}
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/* Counter subdevice (8254) */
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if (board->has_counter) {
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s = &dev->subdevices[subdev];
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s->type = COMEDI_SUBD_COUNTER;
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s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
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s->n_chan = 1;
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s->maxdata = 0xffff;
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s->range_table = &range_unknown;
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s->insn_read = pci171x_counter_insn_read;
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s->insn_write = pci171x_counter_insn_write;
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s->insn_config = pci171x_counter_insn_config;
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comedi_8254_subdevice_init(s, dev->pacer);
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dev->pacer->insn_config = pci171x_insn_counter_config;
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/* counters 1 and 2 are used internally for the pacer */
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comedi_8254_set_busy(dev->pacer, 1, true);
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comedi_8254_set_busy(dev->pacer, 2, true);
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subdev++;
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}
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