net: aquantia: Introduce new AQC devices and capabilities
A number of new AQC devices is going to be released. To support more flexible capabilities management a number of static caps instances is now declared. Devices now are mainly differs by supported speeds, but in future more parameters will be customized. A set of AQC100 devices have fibre media, not twisted pair - this is also reflected in new capabilities definitions. HW level also now directly exports hw_ops for each of A0/B0 hardware. PCI configuration now uses a device configuration table where each device ID is explicitly mapped with hardware OPs and capabilities structures. Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
parent
efe779b749
commit
4948293ff9
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@ -46,6 +46,10 @@
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#define HW_ATL_NIC_NAME "aQuantia AQtion 10Gbit Network Adapter"
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#define HW_ATL_NIC_NAME "aQuantia AQtion 10Gbit Network Adapter"
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#define AQ_HWREV_ANY 0
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#define AQ_HWREV_1 1
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#define AQ_HWREV_2 2
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#define AQ_NIC_RATE_10G BIT(0)
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#define AQ_NIC_RATE_10G BIT(0)
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#define AQ_NIC_RATE_5G BIT(1)
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#define AQ_NIC_RATE_5G BIT(1)
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#define AQ_NIC_RATE_5GSR BIT(2)
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#define AQ_NIC_RATE_5GSR BIT(2)
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@ -23,6 +23,7 @@ struct aq_hw_caps_s {
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u64 hw_features;
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u64 hw_features;
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u64 link_speed_msk;
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u64 link_speed_msk;
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unsigned int hw_priv_flags;
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unsigned int hw_priv_flags;
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u32 media_type;
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u32 rxds;
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u32 rxds;
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u32 txds;
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u32 txds;
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u32 txhwb_alignment;
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u32 txhwb_alignment;
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@ -95,6 +96,9 @@ struct aq_stats_s {
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#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
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#define AQ_NIC_FLAGS_IS_NOT_TX_READY (AQ_NIC_FLAGS_IS_NOT_READY | \
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AQ_NIC_LINK_DOWN)
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AQ_NIC_LINK_DOWN)
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#define AQ_HW_MEDIA_TYPE_TP 1U
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#define AQ_HW_MEDIA_TYPE_FIBRE 2U
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struct aq_hw_s {
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struct aq_hw_s {
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atomic_t flags;
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atomic_t flags;
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struct aq_nic_cfg_s *aq_nic_cfg;
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struct aq_nic_cfg_s *aq_nic_cfg;
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@ -128,11 +132,6 @@ struct aq_hw_ops {
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void (*destroy)(struct aq_hw_s *self);
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void (*destroy)(struct aq_hw_s *self);
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int (*get_hw_caps)(struct aq_hw_s *self,
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struct aq_hw_caps_s *aq_hw_caps,
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unsigned short device,
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unsigned short subsystem_device);
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int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
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int (*hw_ring_tx_xmit)(struct aq_hw_s *self, struct aq_ring_s *aq_ring,
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unsigned int frags);
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unsigned int frags);
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@ -208,7 +208,8 @@ static void aq_nic_polling_timer_cb(struct timer_list *t)
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struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
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struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
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struct aq_pci_func_s *aq_pci_func,
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struct aq_pci_func_s *aq_pci_func,
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unsigned int port,
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unsigned int port,
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const struct aq_hw_ops *aq_hw_ops)
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const struct aq_hw_ops *aq_hw_ops,
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const struct aq_hw_caps_s *aq_hw_caps)
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{
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{
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struct net_device *ndev = NULL;
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struct net_device *ndev = NULL;
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struct aq_nic_s *self = NULL;
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struct aq_nic_s *self = NULL;
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@ -230,16 +231,12 @@ struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
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self->aq_pci_func = aq_pci_func;
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self->aq_pci_func = aq_pci_func;
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self->aq_hw_ops = *aq_hw_ops;
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self->aq_hw_ops = *aq_hw_ops;
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self->aq_hw_caps = *aq_hw_caps;
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self->port = (u8)port;
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self->port = (u8)port;
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self->aq_hw = self->aq_hw_ops.create(aq_pci_func, self->port);
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self->aq_hw = self->aq_hw_ops.create(aq_pci_func, self->port);
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self->aq_hw->aq_nic_cfg = &self->aq_nic_cfg;
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self->aq_hw->aq_nic_cfg = &self->aq_nic_cfg;
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err = self->aq_hw_ops.get_hw_caps(self->aq_hw, &self->aq_hw_caps,
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pdev->device, pdev->subsystem_device);
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if (err < 0)
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goto err_exit;
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aq_nic_cfg_init_defaults(self);
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aq_nic_cfg_init_defaults(self);
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err_exit:
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err_exit:
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@ -92,7 +92,8 @@ static inline struct device *aq_nic_get_dev(struct aq_nic_s *self)
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struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
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struct aq_nic_s *aq_nic_alloc_cold(struct pci_dev *pdev,
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struct aq_pci_func_s *aq_pci_func,
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struct aq_pci_func_s *aq_pci_func,
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unsigned int port,
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unsigned int port,
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const struct aq_hw_ops *aq_hw_ops);
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const struct aq_hw_ops *aq_hw_ops,
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const struct aq_hw_caps_s *aq_hw_caps);
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int aq_nic_ndev_init(struct aq_nic_s *self);
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int aq_nic_ndev_init(struct aq_nic_s *self);
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struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev);
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struct aq_nic_s *aq_nic_alloc_hot(struct net_device *ndev);
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void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
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void aq_nic_set_tx_ring(struct aq_nic_s *self, unsigned int idx,
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@ -60,20 +60,66 @@ static const struct pci_device_id aq_pci_tbl[] = {
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{}
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{}
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};
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};
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const struct aq_board_revision_s hw_atl_boards[] = {
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{ AQ_DEVICE_ID_0001, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
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{ AQ_DEVICE_ID_D100, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc100, },
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{ AQ_DEVICE_ID_D107, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc107, },
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{ AQ_DEVICE_ID_D108, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc108, },
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{ AQ_DEVICE_ID_D109, AQ_HWREV_1, &hw_atl_ops_a0, &hw_atl_a0_caps_aqc109, },
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{ AQ_DEVICE_ID_0001, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
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{ AQ_DEVICE_ID_D100, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc100, },
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{ AQ_DEVICE_ID_D107, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc107, },
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{ AQ_DEVICE_ID_D108, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc108, },
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{ AQ_DEVICE_ID_D109, AQ_HWREV_2, &hw_atl_ops_b0, &hw_atl_b0_caps_aqc109, },
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{ AQ_DEVICE_ID_AQC100, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
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{ AQ_DEVICE_ID_AQC107, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107, },
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{ AQ_DEVICE_ID_AQC108, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108, },
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{ AQ_DEVICE_ID_AQC109, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109, },
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{ AQ_DEVICE_ID_AQC111, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111, },
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{ AQ_DEVICE_ID_AQC112, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112, },
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{ AQ_DEVICE_ID_AQC100S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc100s, },
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{ AQ_DEVICE_ID_AQC107S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc107s, },
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{ AQ_DEVICE_ID_AQC108S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc108s, },
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{ AQ_DEVICE_ID_AQC109S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc109s, },
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{ AQ_DEVICE_ID_AQC111S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111s, },
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{ AQ_DEVICE_ID_AQC112S, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112s, },
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{ AQ_DEVICE_ID_AQC111E, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc111e, },
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{ AQ_DEVICE_ID_AQC112E, AQ_HWREV_ANY, &hw_atl_ops_b1, &hw_atl_b0_caps_aqc112e, },
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};
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MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
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MODULE_DEVICE_TABLE(pci, aq_pci_tbl);
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static const struct aq_hw_ops *aq_pci_probe_get_hw_ops_by_id(struct pci_dev *pdev)
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static int aq_pci_probe_get_hw_by_id(struct pci_dev *pdev,
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const struct aq_hw_ops **ops,
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const struct aq_hw_caps_s **caps)
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{
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{
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const struct aq_hw_ops *ops = NULL;
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int i = 0;
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ops = hw_atl_a0_get_ops_by_id(pdev);
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if (pdev->vendor != PCI_VENDOR_ID_AQUANTIA)
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if (!ops)
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return -EINVAL;
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ops = hw_atl_b0_get_ops_by_id(pdev);
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return ops;
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for (i = 0; i < ARRAY_SIZE(hw_atl_boards); i++) {
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if (hw_atl_boards[i].devid == pdev->device &&
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(hw_atl_boards[i].revision == AQ_HWREV_ANY ||
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hw_atl_boards[i].revision == pdev->revision)) {
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*ops = hw_atl_boards[i].ops;
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*caps = hw_atl_boards[i].caps;
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break;
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}
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}
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if (i == ARRAY_SIZE(hw_atl_boards))
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return -EINVAL;
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return 0;
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}
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}
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struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *aq_hw_ops,
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struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *aq_hw_ops,
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const struct aq_hw_caps_s *aq_hw_caps,
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struct pci_dev *pdev)
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struct pci_dev *pdev)
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{
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{
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struct aq_pci_func_s *self = NULL;
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struct aq_pci_func_s *self = NULL;
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pci_set_drvdata(pdev, self);
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pci_set_drvdata(pdev, self);
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self->pdev = pdev;
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self->pdev = pdev;
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self->aq_hw_caps = *aq_hw_caps;
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err = aq_hw_ops->get_hw_caps(NULL, &self->aq_hw_caps, pdev->device,
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pdev->subsystem_device);
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if (err < 0)
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goto err_exit;
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self->ports = self->aq_hw_caps.ports;
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self->ports = self->aq_hw_caps.ports;
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for (port = 0; port < self->ports; ++port) {
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for (port = 0; port < self->ports; ++port) {
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struct aq_nic_s *aq_nic = aq_nic_alloc_cold(pdev, self,
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struct aq_nic_s *aq_nic = aq_nic_alloc_cold(pdev, self,
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port, aq_hw_ops);
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port, aq_hw_ops,
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aq_hw_caps);
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if (!aq_nic) {
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if (!aq_nic) {
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err = -ENOMEM;
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err = -ENOMEM;
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@ -343,14 +386,17 @@ static int aq_pci_probe(struct pci_dev *pdev,
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const struct pci_device_id *pci_id)
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const struct pci_device_id *pci_id)
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{
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{
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const struct aq_hw_ops *aq_hw_ops = NULL;
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const struct aq_hw_ops *aq_hw_ops = NULL;
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const struct aq_hw_caps_s *aq_hw_caps = NULL;
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struct aq_pci_func_s *aq_pci_func = NULL;
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struct aq_pci_func_s *aq_pci_func = NULL;
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int err = 0;
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int err = 0;
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err = pci_enable_device(pdev);
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err = pci_enable_device(pdev);
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if (err < 0)
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if (err < 0)
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goto err_exit;
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goto err_exit;
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aq_hw_ops = aq_pci_probe_get_hw_ops_by_id(pdev);
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err = aq_pci_probe_get_hw_by_id(pdev, &aq_hw_ops, &aq_hw_caps);
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aq_pci_func = aq_pci_func_alloc(aq_hw_ops, pdev);
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if (err < 0)
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goto err_exit;
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aq_pci_func = aq_pci_func_alloc(aq_hw_ops, aq_hw_caps, pdev);
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if (!aq_pci_func) {
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if (!aq_pci_func) {
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err = -ENOMEM;
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err = -ENOMEM;
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goto err_exit;
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goto err_exit;
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@ -15,8 +15,13 @@
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#include "aq_common.h"
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#include "aq_common.h"
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#include "aq_nic.h"
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#include "aq_nic.h"
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struct aq_pci_func_s *aq_pci_func_alloc(const struct aq_hw_ops *hw_ops,
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struct aq_board_revision_s {
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struct pci_dev *pdev);
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unsigned short devid;
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unsigned short revision;
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const struct aq_hw_ops *ops;
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const struct aq_hw_caps_s *caps;
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};
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int aq_pci_func_init(struct aq_pci_func_s *self);
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int aq_pci_func_init(struct aq_pci_func_s *self);
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int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
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int aq_pci_func_alloc_irq(struct aq_pci_func_s *self, unsigned int i,
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char *name, void *aq_vec,
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char *name, void *aq_vec,
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@ -18,23 +18,67 @@
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#include "hw_atl_llh.h"
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#include "hw_atl_llh.h"
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#include "hw_atl_a0_internal.h"
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#include "hw_atl_a0_internal.h"
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static int hw_atl_a0_get_hw_caps(struct aq_hw_s *self,
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#define DEFAULT_A0_BOARD_BASIC_CAPABILITIES \
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struct aq_hw_caps_s *aq_hw_caps,
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.is_64_dma = true, \
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unsigned short device,
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.msix_irqs = 4U, \
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unsigned short subsystem_device)
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.irq_mask = ~0U, \
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{
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.vecs = HW_ATL_A0_RSS_MAX, \
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memcpy(aq_hw_caps, &hw_atl_a0_hw_caps_, sizeof(*aq_hw_caps));
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.tcs = HW_ATL_A0_TC_MAX, \
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.rxd_alignment = 1U, \
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.rxd_size = HW_ATL_A0_RXD_SIZE, \
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.rxds = 248U, \
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.txd_alignment = 1U, \
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.txd_size = HW_ATL_A0_TXD_SIZE, \
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.txds = 8U * 1024U, \
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.txhwb_alignment = 4096U, \
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.tx_rings = HW_ATL_A0_TX_RINGS, \
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.rx_rings = HW_ATL_A0_RX_RINGS, \
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.hw_features = NETIF_F_HW_CSUM | \
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NETIF_F_RXHASH | \
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NETIF_F_RXCSUM | \
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NETIF_F_SG | \
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NETIF_F_TSO, \
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.hw_priv_flags = IFF_UNICAST_FLT, \
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.flow_control = true, \
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.mtu = HW_ATL_A0_MTU_JUMBO, \
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.mac_regs_count = 88
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if (device == AQ_DEVICE_ID_D108 && subsystem_device == 0x0001)
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const struct aq_hw_caps_s hw_atl_a0_caps_aqc100 = {
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aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_10G;
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DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
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.media_type = AQ_HW_MEDIA_TYPE_FIBRE,
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.link_speed_msk = HW_ATL_A0_RATE_5G |
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HW_ATL_A0_RATE_2G5 |
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HW_ATL_A0_RATE_1G |
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HW_ATL_A0_RATE_100M,
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};
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if (device == AQ_DEVICE_ID_D109 && subsystem_device == 0x0001) {
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const struct aq_hw_caps_s hw_atl_a0_caps_aqc107 = {
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aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_10G;
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DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
|
||||||
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_5G;
|
.media_type = AQ_HW_MEDIA_TYPE_TP,
|
||||||
}
|
.link_speed_msk = HW_ATL_A0_RATE_10G |
|
||||||
|
HW_ATL_A0_RATE_5G |
|
||||||
|
HW_ATL_A0_RATE_2G5 |
|
||||||
|
HW_ATL_A0_RATE_1G |
|
||||||
|
HW_ATL_A0_RATE_100M,
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct aq_hw_caps_s hw_atl_a0_caps_aqc108 = {
|
||||||
|
DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
|
||||||
|
.media_type = AQ_HW_MEDIA_TYPE_TP,
|
||||||
|
.link_speed_msk = HW_ATL_A0_RATE_5G |
|
||||||
|
HW_ATL_A0_RATE_2G5 |
|
||||||
|
HW_ATL_A0_RATE_1G |
|
||||||
|
HW_ATL_A0_RATE_100M,
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
|
||||||
|
DEFAULT_A0_BOARD_BASIC_CAPABILITIES,
|
||||||
|
.media_type = AQ_HW_MEDIA_TYPE_TP,
|
||||||
|
.link_speed_msk = HW_ATL_A0_RATE_2G5 |
|
||||||
|
HW_ATL_A0_RATE_1G |
|
||||||
|
HW_ATL_A0_RATE_100M,
|
||||||
|
};
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func,
|
static struct aq_hw_s *hw_atl_a0_create(struct aq_pci_func_s *aq_pci_func,
|
||||||
unsigned int port)
|
unsigned int port)
|
||||||
|
@ -861,11 +905,9 @@ err_exit:
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct aq_hw_ops hw_atl_ops_ = {
|
const struct aq_hw_ops hw_atl_ops_a0 = {
|
||||||
.create = hw_atl_a0_create,
|
.create = hw_atl_a0_create,
|
||||||
.destroy = hw_atl_a0_destroy,
|
.destroy = hw_atl_a0_destroy,
|
||||||
.get_hw_caps = hw_atl_a0_get_hw_caps,
|
|
||||||
|
|
||||||
.hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
|
.hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
|
||||||
.hw_set_mac_address = hw_atl_a0_hw_mac_addr_set,
|
.hw_set_mac_address = hw_atl_a0_hw_mac_addr_set,
|
||||||
.hw_get_link_status = hw_atl_utils_mpi_get_link_status,
|
.hw_get_link_status = hw_atl_utils_mpi_get_link_status,
|
||||||
|
@ -903,17 +945,3 @@ static const struct aq_hw_ops hw_atl_ops_ = {
|
||||||
.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
|
.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
|
||||||
.hw_get_fw_version = hw_atl_utils_get_fw_version,
|
.hw_get_fw_version = hw_atl_utils_get_fw_version,
|
||||||
};
|
};
|
||||||
|
|
||||||
const struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev)
|
|
||||||
{
|
|
||||||
bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
|
|
||||||
bool is_did_ok = ((pdev->device == AQ_DEVICE_ID_0001) ||
|
|
||||||
(pdev->device == AQ_DEVICE_ID_D100) ||
|
|
||||||
(pdev->device == AQ_DEVICE_ID_D107) ||
|
|
||||||
(pdev->device == AQ_DEVICE_ID_D108) ||
|
|
||||||
(pdev->device == AQ_DEVICE_ID_D109));
|
|
||||||
|
|
||||||
bool is_rev_ok = (pdev->revision == 1U);
|
|
||||||
|
|
||||||
return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
|
|
||||||
}
|
|
||||||
|
|
|
@ -16,6 +16,11 @@
|
||||||
|
|
||||||
#include "../aq_common.h"
|
#include "../aq_common.h"
|
||||||
|
|
||||||
const struct aq_hw_ops *hw_atl_a0_get_ops_by_id(struct pci_dev *pdev);
|
extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc100;
|
||||||
|
extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc107;
|
||||||
|
extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc108;
|
||||||
|
extern const struct aq_hw_caps_s hw_atl_a0_caps_aqc109;
|
||||||
|
|
||||||
|
extern const struct aq_hw_ops hw_atl_ops_a0;
|
||||||
|
|
||||||
#endif /* HW_ATL_A0_H */
|
#endif /* HW_ATL_A0_H */
|
||||||
|
|
|
@ -62,6 +62,12 @@
|
||||||
#define HW_ATL_A0_MPI_SPEED_MSK 0xFFFFU
|
#define HW_ATL_A0_MPI_SPEED_MSK 0xFFFFU
|
||||||
#define HW_ATL_A0_MPI_SPEED_SHIFT 16U
|
#define HW_ATL_A0_MPI_SPEED_SHIFT 16U
|
||||||
|
|
||||||
|
#define HW_ATL_A0_RATE_10G BIT(0)
|
||||||
|
#define HW_ATL_A0_RATE_5G BIT(1)
|
||||||
|
#define HW_ATL_A0_RATE_2G5 BIT(3)
|
||||||
|
#define HW_ATL_A0_RATE_1G BIT(4)
|
||||||
|
#define HW_ATL_A0_RATE_100M BIT(5)
|
||||||
|
|
||||||
#define HW_ATL_A0_TXBUF_MAX 160U
|
#define HW_ATL_A0_TXBUF_MAX 160U
|
||||||
#define HW_ATL_A0_RXBUF_MAX 320U
|
#define HW_ATL_A0_RXBUF_MAX 320U
|
||||||
|
|
||||||
|
@ -82,38 +88,4 @@
|
||||||
|
|
||||||
#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
|
#define HW_ATL_A0_FW_VER_EXPECTED 0x01050006U
|
||||||
|
|
||||||
/* HW layer capabilities */
|
|
||||||
static struct aq_hw_caps_s hw_atl_a0_hw_caps_ = {
|
|
||||||
.ports = 1U,
|
|
||||||
.is_64_dma = true,
|
|
||||||
.msix_irqs = 4U,
|
|
||||||
.irq_mask = ~0U,
|
|
||||||
.vecs = HW_ATL_A0_RSS_MAX,
|
|
||||||
.tcs = HW_ATL_A0_TC_MAX,
|
|
||||||
.rxd_alignment = 1U,
|
|
||||||
.rxd_size = HW_ATL_A0_RXD_SIZE,
|
|
||||||
.rxds = 248U,
|
|
||||||
.txd_alignment = 1U,
|
|
||||||
.txd_size = HW_ATL_A0_TXD_SIZE,
|
|
||||||
.txds = 8U * 1024U,
|
|
||||||
.txhwb_alignment = 4096U,
|
|
||||||
.tx_rings = HW_ATL_A0_TX_RINGS,
|
|
||||||
.rx_rings = HW_ATL_A0_RX_RINGS,
|
|
||||||
.hw_features = NETIF_F_HW_CSUM |
|
|
||||||
NETIF_F_RXCSUM |
|
|
||||||
NETIF_F_RXHASH |
|
|
||||||
NETIF_F_SG |
|
|
||||||
NETIF_F_TSO,
|
|
||||||
.hw_priv_flags = IFF_UNICAST_FLT,
|
|
||||||
.link_speed_msk = (AQ_NIC_RATE_10G |
|
|
||||||
AQ_NIC_RATE_5G |
|
|
||||||
AQ_NIC_RATE_2GS |
|
|
||||||
AQ_NIC_RATE_1G |
|
|
||||||
AQ_NIC_RATE_100M),
|
|
||||||
.flow_control = true,
|
|
||||||
.mtu = HW_ATL_A0_MTU_JUMBO,
|
|
||||||
.mac_regs_count = 88,
|
|
||||||
.fw_ver_expected = HW_ATL_A0_FW_VER_EXPECTED,
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* HW_ATL_A0_INTERNAL_H */
|
#endif /* HW_ATL_A0_INTERNAL_H */
|
||||||
|
|
|
@ -19,23 +19,68 @@
|
||||||
#include "hw_atl_b0_internal.h"
|
#include "hw_atl_b0_internal.h"
|
||||||
#include "hw_atl_llh_internal.h"
|
#include "hw_atl_llh_internal.h"
|
||||||
|
|
||||||
static int hw_atl_b0_get_hw_caps(struct aq_hw_s *self,
|
#define DEFAULT_B0_BOARD_BASIC_CAPABILITIES \
|
||||||
struct aq_hw_caps_s *aq_hw_caps,
|
.is_64_dma = true, \
|
||||||
unsigned short device,
|
.msix_irqs = 4U, \
|
||||||
unsigned short subsystem_device)
|
.irq_mask = ~0U, \
|
||||||
{
|
.vecs = HW_ATL_B0_RSS_MAX, \
|
||||||
memcpy(aq_hw_caps, &hw_atl_b0_hw_caps_, sizeof(*aq_hw_caps));
|
.tcs = HW_ATL_B0_TC_MAX, \
|
||||||
|
.rxd_alignment = 1U, \
|
||||||
|
.rxd_size = HW_ATL_B0_RXD_SIZE, \
|
||||||
|
.rxds = 4U * 1024U, \
|
||||||
|
.txd_alignment = 1U, \
|
||||||
|
.txd_size = HW_ATL_B0_TXD_SIZE, \
|
||||||
|
.txds = 8U * 1024U, \
|
||||||
|
.txhwb_alignment = 4096U, \
|
||||||
|
.tx_rings = HW_ATL_B0_TX_RINGS, \
|
||||||
|
.rx_rings = HW_ATL_B0_RX_RINGS, \
|
||||||
|
.hw_features = NETIF_F_HW_CSUM | \
|
||||||
|
NETIF_F_RXCSUM | \
|
||||||
|
NETIF_F_RXHASH | \
|
||||||
|
NETIF_F_SG | \
|
||||||
|
NETIF_F_TSO | \
|
||||||
|
NETIF_F_LRO, \
|
||||||
|
.hw_priv_flags = IFF_UNICAST_FLT, \
|
||||||
|
.flow_control = true, \
|
||||||
|
.mtu = HW_ATL_B0_MTU_JUMBO, \
|
||||||
|
.mac_regs_count = 88
|
||||||
|
|
||||||
if (device == AQ_DEVICE_ID_D108 && subsystem_device == 0x0001)
|
const struct aq_hw_caps_s hw_atl_b0_caps_aqc100 = {
|
||||||
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_10G;
|
DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
|
||||||
|
.media_type = AQ_HW_MEDIA_TYPE_FIBRE,
|
||||||
|
.link_speed_msk = HW_ATL_B0_RATE_10G |
|
||||||
|
HW_ATL_B0_RATE_5G |
|
||||||
|
HW_ATL_B0_RATE_2G5 |
|
||||||
|
HW_ATL_B0_RATE_1G |
|
||||||
|
HW_ATL_B0_RATE_100M,
|
||||||
|
};
|
||||||
|
|
||||||
if (device == AQ_DEVICE_ID_D109 && subsystem_device == 0x0001) {
|
const struct aq_hw_caps_s hw_atl_b0_caps_aqc107 = {
|
||||||
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_10G;
|
DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
|
||||||
aq_hw_caps->link_speed_msk &= ~AQ_NIC_RATE_5G;
|
.media_type = AQ_HW_MEDIA_TYPE_TP,
|
||||||
}
|
.link_speed_msk = HW_ATL_B0_RATE_10G |
|
||||||
|
HW_ATL_B0_RATE_5G |
|
||||||
|
HW_ATL_B0_RATE_2G5 |
|
||||||
|
HW_ATL_B0_RATE_1G |
|
||||||
|
HW_ATL_B0_RATE_100M,
|
||||||
|
};
|
||||||
|
|
||||||
return 0;
|
const struct aq_hw_caps_s hw_atl_b0_caps_aqc108 = {
|
||||||
}
|
DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
|
||||||
|
.media_type = AQ_HW_MEDIA_TYPE_TP,
|
||||||
|
.link_speed_msk = HW_ATL_B0_RATE_5G |
|
||||||
|
HW_ATL_B0_RATE_2G5 |
|
||||||
|
HW_ATL_B0_RATE_1G |
|
||||||
|
HW_ATL_B0_RATE_100M,
|
||||||
|
};
|
||||||
|
|
||||||
|
const struct aq_hw_caps_s hw_atl_b0_caps_aqc109 = {
|
||||||
|
DEFAULT_B0_BOARD_BASIC_CAPABILITIES,
|
||||||
|
.media_type = AQ_HW_MEDIA_TYPE_TP,
|
||||||
|
.link_speed_msk = HW_ATL_B0_RATE_2G5 |
|
||||||
|
HW_ATL_B0_RATE_1G |
|
||||||
|
HW_ATL_B0_RATE_100M,
|
||||||
|
};
|
||||||
|
|
||||||
static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func,
|
static struct aq_hw_s *hw_atl_b0_create(struct aq_pci_func_s *aq_pci_func,
|
||||||
unsigned int port)
|
unsigned int port)
|
||||||
|
@ -935,11 +980,9 @@ err_exit:
|
||||||
return err;
|
return err;
|
||||||
}
|
}
|
||||||
|
|
||||||
static const struct aq_hw_ops hw_atl_ops_ = {
|
const struct aq_hw_ops hw_atl_ops_b0 = {
|
||||||
.create = hw_atl_b0_create,
|
.create = hw_atl_b0_create,
|
||||||
.destroy = hw_atl_b0_destroy,
|
.destroy = hw_atl_b0_destroy,
|
||||||
.get_hw_caps = hw_atl_b0_get_hw_caps,
|
|
||||||
|
|
||||||
.hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
|
.hw_get_mac_permanent = hw_atl_utils_get_mac_permanent,
|
||||||
.hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
|
.hw_set_mac_address = hw_atl_b0_hw_mac_addr_set,
|
||||||
.hw_get_link_status = hw_atl_utils_mpi_get_link_status,
|
.hw_get_link_status = hw_atl_utils_mpi_get_link_status,
|
||||||
|
@ -977,17 +1020,3 @@ static const struct aq_hw_ops hw_atl_ops_ = {
|
||||||
.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
|
.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
|
||||||
.hw_get_fw_version = hw_atl_utils_get_fw_version,
|
.hw_get_fw_version = hw_atl_utils_get_fw_version,
|
||||||
};
|
};
|
||||||
|
|
||||||
const struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev)
|
|
||||||
{
|
|
||||||
bool is_vid_ok = (pdev->vendor == PCI_VENDOR_ID_AQUANTIA);
|
|
||||||
bool is_did_ok = ((pdev->device == AQ_DEVICE_ID_0001) ||
|
|
||||||
(pdev->device == AQ_DEVICE_ID_D100) ||
|
|
||||||
(pdev->device == AQ_DEVICE_ID_D107) ||
|
|
||||||
(pdev->device == AQ_DEVICE_ID_D108) ||
|
|
||||||
(pdev->device == AQ_DEVICE_ID_D109));
|
|
||||||
|
|
||||||
bool is_rev_ok = (pdev->revision == 2U);
|
|
||||||
|
|
||||||
return (is_vid_ok && is_did_ok && is_rev_ok) ? &hw_atl_ops_ : NULL;
|
|
||||||
}
|
|
||||||
|
|
|
@ -16,6 +16,27 @@
|
||||||
|
|
||||||
#include "../aq_common.h"
|
#include "../aq_common.h"
|
||||||
|
|
||||||
const struct aq_hw_ops *hw_atl_b0_get_ops_by_id(struct pci_dev *pdev);
|
extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc100;
|
||||||
|
extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc107;
|
||||||
|
extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc108;
|
||||||
|
extern const struct aq_hw_caps_s hw_atl_b0_caps_aqc109;
|
||||||
|
|
||||||
|
#define hw_atl_b0_caps_aqc111 hw_atl_b0_caps_aqc108
|
||||||
|
#define hw_atl_b0_caps_aqc112 hw_atl_b0_caps_aqc109
|
||||||
|
|
||||||
|
#define hw_atl_b0_caps_aqc100s hw_atl_b0_caps_aqc100
|
||||||
|
#define hw_atl_b0_caps_aqc107s hw_atl_b0_caps_aqc107
|
||||||
|
#define hw_atl_b0_caps_aqc108s hw_atl_b0_caps_aqc108
|
||||||
|
#define hw_atl_b0_caps_aqc109s hw_atl_b0_caps_aqc109
|
||||||
|
|
||||||
|
#define hw_atl_b0_caps_aqc111s hw_atl_b0_caps_aqc108
|
||||||
|
#define hw_atl_b0_caps_aqc112s hw_atl_b0_caps_aqc109
|
||||||
|
|
||||||
|
#define hw_atl_b0_caps_aqc111e hw_atl_b0_caps_aqc108
|
||||||
|
#define hw_atl_b0_caps_aqc112e hw_atl_b0_caps_aqc109
|
||||||
|
|
||||||
|
extern const struct aq_hw_ops hw_atl_ops_b0;
|
||||||
|
|
||||||
|
#define hw_atl_ops_b1 hw_atl_ops_b0
|
||||||
|
|
||||||
#endif /* HW_ATL_B0_H */
|
#endif /* HW_ATL_B0_H */
|
||||||
|
|
|
@ -67,6 +67,12 @@
|
||||||
#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU
|
#define HW_ATL_B0_MPI_SPEED_MSK 0xFFFFU
|
||||||
#define HW_ATL_B0_MPI_SPEED_SHIFT 16U
|
#define HW_ATL_B0_MPI_SPEED_SHIFT 16U
|
||||||
|
|
||||||
|
#define HW_ATL_B0_RATE_10G BIT(0)
|
||||||
|
#define HW_ATL_B0_RATE_5G BIT(1)
|
||||||
|
#define HW_ATL_B0_RATE_2G5 BIT(3)
|
||||||
|
#define HW_ATL_B0_RATE_1G BIT(4)
|
||||||
|
#define HW_ATL_B0_RATE_100M BIT(5)
|
||||||
|
|
||||||
#define HW_ATL_B0_TXBUF_MAX 160U
|
#define HW_ATL_B0_TXBUF_MAX 160U
|
||||||
#define HW_ATL_B0_RXBUF_MAX 320U
|
#define HW_ATL_B0_RXBUF_MAX 320U
|
||||||
|
|
||||||
|
@ -137,38 +143,5 @@
|
||||||
#define HW_ATL_INTR_MODER_MIN 0xFF
|
#define HW_ATL_INTR_MODER_MIN 0xFF
|
||||||
|
|
||||||
/* HW layer capabilities */
|
/* HW layer capabilities */
|
||||||
static struct aq_hw_caps_s hw_atl_b0_hw_caps_ = {
|
|
||||||
.ports = 1U,
|
|
||||||
.is_64_dma = true,
|
|
||||||
.msix_irqs = 4U,
|
|
||||||
.irq_mask = ~0U,
|
|
||||||
.vecs = HW_ATL_B0_RSS_MAX,
|
|
||||||
.tcs = HW_ATL_B0_TC_MAX,
|
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||||||
.rxd_alignment = 1U,
|
|
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.rxd_size = HW_ATL_B0_RXD_SIZE,
|
|
||||||
.rxds = 8U * 1024U,
|
|
||||||
.txd_alignment = 1U,
|
|
||||||
.txd_size = HW_ATL_B0_TXD_SIZE,
|
|
||||||
.txds = 8U * 1024U,
|
|
||||||
.txhwb_alignment = 4096U,
|
|
||||||
.tx_rings = HW_ATL_B0_TX_RINGS,
|
|
||||||
.rx_rings = HW_ATL_B0_RX_RINGS,
|
|
||||||
.hw_features = NETIF_F_HW_CSUM |
|
|
||||||
NETIF_F_RXCSUM |
|
|
||||||
NETIF_F_RXHASH |
|
|
||||||
NETIF_F_SG |
|
|
||||||
NETIF_F_TSO |
|
|
||||||
NETIF_F_LRO,
|
|
||||||
.hw_priv_flags = IFF_UNICAST_FLT,
|
|
||||||
.link_speed_msk = (AQ_NIC_RATE_10G |
|
|
||||||
AQ_NIC_RATE_5G |
|
|
||||||
AQ_NIC_RATE_2GS |
|
|
||||||
AQ_NIC_RATE_1G |
|
|
||||||
AQ_NIC_RATE_100M),
|
|
||||||
.flow_control = true,
|
|
||||||
.mtu = HW_ATL_B0_MTU_JUMBO,
|
|
||||||
.mac_regs_count = 88,
|
|
||||||
.fw_ver_expected = HW_ATL_B0_FW_VER_EXPECTED,
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif /* HW_ATL_B0_INTERNAL_H */
|
#endif /* HW_ATL_B0_INTERNAL_H */
|
||||||
|
|
Loading…
Reference in New Issue