x86: make 32bit support per_cpu vector
so we can merge io_apic_32.c and io_apic_64.c v2: Use cpu_online_map as target cpus for bigsmp, just like 64-bit is doing. Also remove some unused TARGET_CPUS macro. v3: need to check if desc is null in smp_irq_move_cleanup also migration needs to reset vector too, so copy __target_IO_APIC_irq from 64bit. (the duplication will go away once the two files are unified.) Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
parent
199751d715
commit
497c9a195d
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@ -629,7 +629,7 @@ ENTRY(interrupt)
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ENTRY(irq_entries_start)
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ENTRY(irq_entries_start)
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RING0_INT_FRAME
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RING0_INT_FRAME
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vector=0
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vector=0
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.rept NR_IRQS
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.rept NR_VECTORS
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ALIGN
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ALIGN
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.if vector
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.if vector
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CFI_ADJUST_CFA_OFFSET -4
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CFI_ADJUST_CFA_OFFSET -4
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File diff suppressed because it is too large
Load Diff
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@ -223,21 +223,25 @@ unsigned int do_IRQ(struct pt_regs *regs)
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{
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{
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struct pt_regs *old_regs;
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struct pt_regs *old_regs;
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/* high bit used in ret_from_ code */
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/* high bit used in ret_from_ code */
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int overflow, irq = ~regs->orig_ax;
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int overflow;
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unsigned vector = ~regs->orig_ax;
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struct irq_desc *desc;
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struct irq_desc *desc;
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unsigned irq;
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desc = irq_to_desc(irq);
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if (unlikely(!desc)) {
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printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
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__func__, irq);
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BUG();
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}
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old_regs = set_irq_regs(regs);
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old_regs = set_irq_regs(regs);
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irq_enter();
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irq_enter();
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irq = __get_cpu_var(vector_irq)[vector];
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overflow = check_stack_overflow();
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overflow = check_stack_overflow();
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desc = irq_to_desc(irq);
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if (unlikely(!desc)) {
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printk(KERN_EMERG "%s: cannot handle IRQ %d vector %#x\n",
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__func__, irq, vector);
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BUG();
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}
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if (!execute_on_irq_stack(overflow, desc, irq)) {
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if (!execute_on_irq_stack(overflow, desc, irq)) {
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if (unlikely(overflow))
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if (unlikely(overflow))
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print_stack_overflow();
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print_stack_overflow();
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@ -90,6 +90,27 @@ static struct irqaction irq2 = {
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.name = "cascade",
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.name = "cascade",
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};
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};
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DEFINE_PER_CPU(vector_irq_t, vector_irq) = {
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[0 ... IRQ0_VECTOR - 1] = -1,
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[IRQ0_VECTOR] = 0,
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[IRQ1_VECTOR] = 1,
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[IRQ2_VECTOR] = 2,
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[IRQ3_VECTOR] = 3,
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[IRQ4_VECTOR] = 4,
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[IRQ5_VECTOR] = 5,
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[IRQ6_VECTOR] = 6,
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[IRQ7_VECTOR] = 7,
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[IRQ8_VECTOR] = 8,
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[IRQ9_VECTOR] = 9,
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[IRQ10_VECTOR] = 10,
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[IRQ11_VECTOR] = 11,
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[IRQ12_VECTOR] = 12,
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[IRQ13_VECTOR] = 13,
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[IRQ14_VECTOR] = 14,
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[IRQ15_VECTOR] = 15,
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[IRQ15_VECTOR + 1 ... NR_VECTORS - 1] = -1
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};
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/* Overridden in paravirt.c */
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/* Overridden in paravirt.c */
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void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
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void init_IRQ(void) __attribute__((weak, alias("native_init_IRQ")));
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@ -105,22 +126,14 @@ void __init native_init_IRQ(void)
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* us. (some of these will be overridden and become
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* us. (some of these will be overridden and become
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* 'special' SMP interrupts)
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* 'special' SMP interrupts)
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*/
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*/
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for (i = 0; i < (NR_VECTORS - FIRST_EXTERNAL_VECTOR); i++) {
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for (i = FIRST_EXTERNAL_VECTOR; i < NR_VECTORS; i++) {
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int vector = FIRST_EXTERNAL_VECTOR + i;
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if (i >= nr_irqs)
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break;
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/* SYSCALL_VECTOR was reserved in trap_init. */
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/* SYSCALL_VECTOR was reserved in trap_init. */
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if (!test_bit(vector, used_vectors))
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if (i != SYSCALL_VECTOR)
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set_intr_gate(vector, interrupt[i]);
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set_intr_gate(i, interrupt[i]);
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}
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}
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_SMP)
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/*
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* IRQ0 must be given a fixed assignment and initialized,
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* because it's used before the IO-APIC is set up.
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*/
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set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]);
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#if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_SMP)
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/*
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/*
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* The reschedule interrupt is a CPU-to-CPU reschedule-helper
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* The reschedule interrupt is a CPU-to-CPU reschedule-helper
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* IPI, driven by wakeup.
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* IPI, driven by wakeup.
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@ -135,6 +148,9 @@ void __init native_init_IRQ(void)
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/* IPI for single call function */
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/* IPI for single call function */
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set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR, call_function_single_interrupt);
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set_intr_gate(CALL_FUNCTION_SINGLE_VECTOR, call_function_single_interrupt);
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/* Low priority IPI to cleanup after moving an irq */
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set_intr_gate(IRQ_MOVE_CLEANUP_VECTOR, irq_move_cleanup_interrupt);
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#endif
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#endif
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#ifdef CONFIG_X86_LOCAL_APIC
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#ifdef CONFIG_X86_LOCAL_APIC
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@ -168,3 +184,4 @@ void __init native_init_IRQ(void)
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irq_ctx_init(smp_processor_id());
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irq_ctx_init(smp_processor_id());
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}
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}
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@ -582,7 +582,7 @@ static void __init lguest_init_IRQ(void)
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for (i = 0; i < LGUEST_IRQS; i++) {
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for (i = 0; i < LGUEST_IRQS; i++) {
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int vector = FIRST_EXTERNAL_VECTOR + i;
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int vector = FIRST_EXTERNAL_VECTOR + i;
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if (vector != SYSCALL_VECTOR) {
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if (vector != SYSCALL_VECTOR) {
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set_intr_gate(vector, interrupt[i]);
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set_intr_gate(vector, interrupt[vector]);
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set_irq_chip_and_handler_name(i, &lguest_irq_controller,
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set_irq_chip_and_handler_name(i, &lguest_irq_controller,
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handle_level_irq,
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handle_level_irq,
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"level");
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"level");
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@ -41,6 +41,10 @@ static const struct dmi_system_id bigsmp_dmi_table[] = {
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{ }
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{ }
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};
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};
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static cpumask_t vector_allocation_domain(int cpu)
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{
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return cpumask_of_cpu(cpu);
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}
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static int probe_bigsmp(void)
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static int probe_bigsmp(void)
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{
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{
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@ -75,4 +75,18 @@ static int __init acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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}
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}
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#endif
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#endif
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static cpumask_t vector_allocation_domain(int cpu)
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{
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/* Careful. Some cpus do not strictly honor the set of cpus
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* specified in the interrupt destination when using lowest
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* priority interrupt delivery mode.
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*
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* In particular there was a hyperthreading cpu observed to
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* deliver interrupts to the wrong hyperthread when only one
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* hyperthread was specified in the interrupt desitination.
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*/
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cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
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return domain;
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}
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struct genapic __initdata_refok apic_es7000 = APIC_INIT("es7000", probe_es7000);
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struct genapic __initdata_refok apic_es7000 = APIC_INIT("es7000", probe_es7000);
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@ -38,4 +38,18 @@ static int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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return 0;
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return 0;
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}
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}
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static cpumask_t vector_allocation_domain(int cpu)
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{
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/* Careful. Some cpus do not strictly honor the set of cpus
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* specified in the interrupt destination when using lowest
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* priority interrupt delivery mode.
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*
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* In particular there was a hyperthreading cpu observed to
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* deliver interrupts to the wrong hyperthread when only one
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* hyperthread was specified in the interrupt desitination.
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*/
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cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
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return domain;
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}
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struct genapic apic_numaq = APIC_INIT("NUMAQ", probe_numaq);
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struct genapic apic_numaq = APIC_INIT("NUMAQ", probe_numaq);
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@ -23,4 +23,18 @@ static int probe_summit(void)
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return 0;
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return 0;
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}
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}
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static cpumask_t vector_allocation_domain(int cpu)
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{
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/* Careful. Some cpus do not strictly honor the set of cpus
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* specified in the interrupt destination when using lowest
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* priority interrupt delivery mode.
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*
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* In particular there was a hyperthreading cpu observed to
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* deliver interrupts to the wrong hyperthread when only one
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* hyperthread was specified in the interrupt desitination.
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*/
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cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
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return domain;
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}
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struct genapic apic_summit = APIC_INIT("summit", probe_summit);
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struct genapic apic_summit = APIC_INIT("summit", probe_summit);
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@ -9,22 +9,17 @@ static inline int apic_id_registered(void)
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return (1);
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return (1);
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}
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}
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/* Round robin the irqs amoung the online cpus */
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static inline cpumask_t target_cpus(void)
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static inline cpumask_t target_cpus(void)
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{
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{
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static unsigned long cpu = NR_CPUS;
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#ifdef CONFIG_SMP
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do {
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return cpu_online_map;
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if (cpu >= NR_CPUS)
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#else
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cpu = first_cpu(cpu_online_map);
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return cpumask_of_cpu(0);
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else
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#endif
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cpu = next_cpu(cpu, cpu_online_map);
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} while (cpu >= NR_CPUS);
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return cpumask_of_cpu(cpu);
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}
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}
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#undef APIC_DEST_LOGICAL
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#undef APIC_DEST_LOGICAL
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#define APIC_DEST_LOGICAL 0
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#define APIC_DEST_LOGICAL 0
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#define TARGET_CPUS (target_cpus())
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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#define APIC_DFR_VALUE (APIC_DFR_FLAT)
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#define INT_DELIVERY_MODE (dest_Fixed)
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#define INT_DELIVERY_MODE (dest_Fixed)
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#define INT_DEST_MODE (0) /* phys delivery to target proc */
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#define INT_DEST_MODE (0) /* phys delivery to target proc */
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@ -17,7 +17,6 @@ static inline cpumask_t target_cpus(void)
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return cpumask_of_cpu(smp_processor_id());
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return cpumask_of_cpu(smp_processor_id());
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#endif
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#endif
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}
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}
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#define TARGET_CPUS (target_cpus())
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#if defined CONFIG_ES7000_CLUSTERED_APIC
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#if defined CONFIG_ES7000_CLUSTERED_APIC
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#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
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#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
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@ -81,7 +80,7 @@ static inline void setup_apic_routing(void)
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int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
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int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
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printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
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printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
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(apic_version[apic] == 0x14) ?
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(apic_version[apic] == 0x14) ?
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"Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(TARGET_CPUS)[0]);
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"Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(target_cpus())[0]);
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}
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}
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static inline int multi_timer_check(int apic, int irq)
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static inline int multi_timer_check(int apic, int irq)
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@ -57,6 +57,7 @@ struct genapic {
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unsigned (*get_apic_id)(unsigned long x);
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unsigned (*get_apic_id)(unsigned long x);
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unsigned long apic_id_mask;
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unsigned long apic_id_mask;
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unsigned int (*cpu_mask_to_apicid)(cpumask_t cpumask);
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unsigned int (*cpu_mask_to_apicid)(cpumask_t cpumask);
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cpumask_t (*vector_allocation_domain)(int cpu);
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#ifdef CONFIG_SMP
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#ifdef CONFIG_SMP
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/* ipi */
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/* ipi */
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@ -104,6 +105,7 @@ struct genapic {
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APICFUNC(get_apic_id) \
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APICFUNC(get_apic_id) \
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.apic_id_mask = APIC_ID_MASK, \
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.apic_id_mask = APIC_ID_MASK, \
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APICFUNC(cpu_mask_to_apicid) \
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APICFUNC(cpu_mask_to_apicid) \
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APICFUNC(vector_allocation_domain) \
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APICFUNC(acpi_madt_oem_check) \
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APICFUNC(acpi_madt_oem_check) \
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IPIFUNC(send_IPI_mask) \
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IPIFUNC(send_IPI_mask) \
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IPIFUNC(send_IPI_allbutself) \
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IPIFUNC(send_IPI_allbutself) \
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@ -116,12 +116,12 @@ extern asmlinkage void smp_invalidate_interrupt(struct pt_regs *);
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#ifdef CONFIG_X86_32
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#ifdef CONFIG_X86_32
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extern void (*const interrupt[NR_IRQS])(void);
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extern void (*const interrupt[NR_IRQS])(void);
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#else
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typedef int vector_irq_t[NR_VECTORS];
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DECLARE_PER_CPU(vector_irq_t, vector_irq);
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#endif
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#endif
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#if defined(CONFIG_X86_IO_APIC) && defined(CONFIG_X86_64)
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typedef int vector_irq_t[NR_VECTORS];
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DECLARE_PER_CPU(vector_irq_t, vector_irq);
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#ifdef CONFIG_X86_IO_APIC
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extern void lock_vector_lock(void);
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extern void lock_vector_lock(void);
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extern void unlock_vector_lock(void);
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extern void unlock_vector_lock(void);
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extern void __setup_vector_irq(int cpu);
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extern void __setup_vector_irq(int cpu);
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@ -19,19 +19,14 @@
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/*
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/*
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* Reserve the lowest usable priority level 0x20 - 0x2f for triggering
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* Reserve the lowest usable priority level 0x20 - 0x2f for triggering
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* cleanup after irq migration on 64 bit.
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* cleanup after irq migration.
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*/
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*/
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#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
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#define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR
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/*
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/*
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* Vectors 0x20-0x2f are used for ISA interrupts on 32 bit.
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* Vectors 0x30-0x3f are used for ISA interrupts.
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* Vectors 0x30-0x3f are used for ISA interrupts on 64 bit.
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*/
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*/
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#ifdef CONFIG_X86_32
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#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR)
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#else
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#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
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#define IRQ0_VECTOR (FIRST_EXTERNAL_VECTOR + 0x10)
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#endif
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#define IRQ1_VECTOR (IRQ0_VECTOR + 1)
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#define IRQ1_VECTOR (IRQ0_VECTOR + 1)
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#define IRQ2_VECTOR (IRQ0_VECTOR + 2)
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#define IRQ2_VECTOR (IRQ0_VECTOR + 2)
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#define IRQ3_VECTOR (IRQ0_VECTOR + 3)
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#define IRQ3_VECTOR (IRQ0_VECTOR + 3)
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@ -96,11 +91,7 @@
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* start at 0x31(0x41) to spread out vectors evenly between priority
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* start at 0x31(0x41) to spread out vectors evenly between priority
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* levels. (0x80 is the syscall vector)
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* levels. (0x80 is the syscall vector)
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*/
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*/
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#ifdef CONFIG_X86_32
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#define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
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# define FIRST_DEVICE_VECTOR 0x31
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#else
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# define FIRST_DEVICE_VECTOR (IRQ15_VECTOR + 2)
|
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||||||
#endif
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||||||
|
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||||||
#define NR_VECTORS 256
|
#define NR_VECTORS 256
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||||||
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||||||
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|
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@ -14,6 +14,7 @@ BUILD_INTERRUPT(reschedule_interrupt,RESCHEDULE_VECTOR)
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||||||
BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
|
BUILD_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
|
||||||
BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
|
BUILD_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
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||||||
BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
|
BUILD_INTERRUPT(call_function_single_interrupt,CALL_FUNCTION_SINGLE_VECTOR)
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||||||
|
BUILD_INTERRUPT(irq_move_cleanup_interrupt,IRQ_MOVE_CLEANUP_VECTOR)
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -85,6 +85,20 @@ static inline int apicid_to_node(int logical_apicid)
|
||||||
return 0;
|
return 0;
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
static inline cpumask_t vector_allocation_domain(int cpu)
|
||||||
|
{
|
||||||
|
/* Careful. Some cpus do not strictly honor the set of cpus
|
||||||
|
* specified in the interrupt destination when using lowest
|
||||||
|
* priority interrupt delivery mode.
|
||||||
|
*
|
||||||
|
* In particular there was a hyperthreading cpu observed to
|
||||||
|
* deliver interrupts to the wrong hyperthread when only one
|
||||||
|
* hyperthread was specified in the interrupt desitination.
|
||||||
|
*/
|
||||||
|
cpumask_t domain = { { [0] = APIC_ALL_CPUS, } };
|
||||||
|
return domain;
|
||||||
|
}
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
|
static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
|
||||||
|
@ -138,6 +152,5 @@ static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
|
||||||
static inline void enable_apic_mode(void)
|
static inline void enable_apic_mode(void)
|
||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
#endif /* CONFIG_X86_LOCAL_APIC */
|
#endif /* CONFIG_X86_LOCAL_APIC */
|
||||||
#endif /* ASM_X86__MACH_DEFAULT__MACH_APIC_H */
|
#endif /* ASM_X86__MACH_DEFAULT__MACH_APIC_H */
|
||||||
|
|
|
@ -24,6 +24,7 @@
|
||||||
#define check_phys_apicid_present (genapic->check_phys_apicid_present)
|
#define check_phys_apicid_present (genapic->check_phys_apicid_present)
|
||||||
#define check_apicid_used (genapic->check_apicid_used)
|
#define check_apicid_used (genapic->check_apicid_used)
|
||||||
#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
|
#define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
|
||||||
|
#define vector_allocation_domain (genapic->vector_allocation_domain)
|
||||||
#define enable_apic_mode (genapic->enable_apic_mode)
|
#define enable_apic_mode (genapic->enable_apic_mode)
|
||||||
#define phys_pkg_id (genapic->phys_pkg_id)
|
#define phys_pkg_id (genapic->phys_pkg_id)
|
||||||
|
|
||||||
|
|
|
@ -12,8 +12,6 @@ static inline cpumask_t target_cpus(void)
|
||||||
return CPU_MASK_ALL;
|
return CPU_MASK_ALL;
|
||||||
}
|
}
|
||||||
|
|
||||||
#define TARGET_CPUS (target_cpus())
|
|
||||||
|
|
||||||
#define NO_BALANCE_IRQ (1)
|
#define NO_BALANCE_IRQ (1)
|
||||||
#define esr_disable (1)
|
#define esr_disable (1)
|
||||||
|
|
||||||
|
|
|
@ -22,7 +22,6 @@ static inline cpumask_t target_cpus(void)
|
||||||
*/
|
*/
|
||||||
return cpumask_of_cpu(0);
|
return cpumask_of_cpu(0);
|
||||||
}
|
}
|
||||||
#define TARGET_CPUS (target_cpus())
|
|
||||||
|
|
||||||
#define INT_DELIVERY_MODE (dest_LowestPrio)
|
#define INT_DELIVERY_MODE (dest_LowestPrio)
|
||||||
#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
|
#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
|
||||||
|
|
Loading…
Reference in New Issue