clk: ingenic: Allow divider value to be divided
The JZ4780's MSC clock divider registers multiply the clock divider by 2. This means that MMC devices run at half their expected speed. Add the ability to divide the clock divider in order to solve this. Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-clk@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
parent
5707291c6c
commit
4afe2d1a6e
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@ -325,6 +325,7 @@ ingenic_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
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div = (div_reg >> clk_info->div.shift) &
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div = (div_reg >> clk_info->div.shift) &
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GENMASK(clk_info->div.bits - 1, 0);
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GENMASK(clk_info->div.bits - 1, 0);
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div += 1;
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div += 1;
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div *= clk_info->div.div;
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rate /= div;
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rate /= div;
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}
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}
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@ -345,6 +346,14 @@ ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info,
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div = min_t(unsigned, div, 1 << clk_info->div.bits);
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div = min_t(unsigned, div, 1 << clk_info->div.bits);
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div = max_t(unsigned, div, 1);
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div = max_t(unsigned, div, 1);
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/*
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* If the divider value itself must be divided before being written to
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* the divider register, we must ensure we don't have any bits set that
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* would be lost as a result of doing so.
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*/
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div /= clk_info->div.div;
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div *= clk_info->div.div;
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return div;
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return div;
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}
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}
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@ -395,7 +404,7 @@ ingenic_clk_set_rate(struct clk_hw *hw, unsigned long req_rate,
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/* update the divide */
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/* update the divide */
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mask = GENMASK(clk_info->div.bits - 1, 0);
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mask = GENMASK(clk_info->div.bits - 1, 0);
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reg &= ~(mask << clk_info->div.shift);
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reg &= ~(mask << clk_info->div.shift);
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reg |= (div - 1) << clk_info->div.shift;
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reg |= ((div / clk_info->div.div) - 1) << clk_info->div.shift;
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/* clear the stop bit */
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/* clear the stop bit */
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if (clk_info->div.stop_bit != -1)
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if (clk_info->div.stop_bit != -1)
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@ -76,8 +76,11 @@ struct ingenic_cgu_mux_info {
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/**
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/**
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* struct ingenic_cgu_div_info - information about a divider
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* struct ingenic_cgu_div_info - information about a divider
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* @reg: offset of the divider control register within the CGU
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* @reg: offset of the divider control register within the CGU
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* @shift: number of bits to shift the divide value by (ie. the index of
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* @shift: number of bits to left shift the divide value by (ie. the index of
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* the lowest bit of the divide value within its control register)
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* the lowest bit of the divide value within its control register)
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* @div: number of bits to divide the divider value by (i.e. if the
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* effective divider value is the value written to the register
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* multiplied by some constant)
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* @bits: the size of the divide value in bits
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* @bits: the size of the divide value in bits
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* @ce_bit: the index of the change enable bit within reg, or -1 if there
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* @ce_bit: the index of the change enable bit within reg, or -1 if there
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* isn't one
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* isn't one
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@ -87,6 +90,7 @@ struct ingenic_cgu_mux_info {
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struct ingenic_cgu_div_info {
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struct ingenic_cgu_div_info {
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unsigned reg;
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unsigned reg;
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u8 shift;
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u8 shift;
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u8 div;
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u8 bits;
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u8 bits;
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s8 ce_bit;
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s8 ce_bit;
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s8 busy_bit;
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s8 busy_bit;
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@ -90,51 +90,51 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
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[JZ4740_CLK_PLL_HALF] = {
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[JZ4740_CLK_PLL_HALF] = {
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"pll half", CGU_CLK_DIV,
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"pll half", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 21, 1, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
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},
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},
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[JZ4740_CLK_CCLK] = {
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[JZ4740_CLK_CCLK] = {
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"cclk", CGU_CLK_DIV,
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"cclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 0, 4, 22, -1, -1 },
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.div = { CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1 },
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},
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},
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[JZ4740_CLK_HCLK] = {
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[JZ4740_CLK_HCLK] = {
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"hclk", CGU_CLK_DIV,
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"hclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 4, 4, 22, -1, -1 },
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.div = { CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1 },
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},
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},
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[JZ4740_CLK_PCLK] = {
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[JZ4740_CLK_PCLK] = {
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"pclk", CGU_CLK_DIV,
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"pclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 8, 4, 22, -1, -1 },
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.div = { CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1 },
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},
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},
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[JZ4740_CLK_MCLK] = {
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[JZ4740_CLK_MCLK] = {
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"mclk", CGU_CLK_DIV,
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"mclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.parents = { JZ4740_CLK_PLL, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 12, 4, 22, -1, -1 },
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.div = { CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1 },
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},
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},
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[JZ4740_CLK_LCD] = {
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[JZ4740_CLK_LCD] = {
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"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
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"lcd", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 16, 5, 22, -1, -1 },
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.div = { CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1 },
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.gate = { CGU_REG_CLKGR, 10 },
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.gate = { CGU_REG_CLKGR, 10 },
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},
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},
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[JZ4740_CLK_LCD_PCLK] = {
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[JZ4740_CLK_LCD_PCLK] = {
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"lcd_pclk", CGU_CLK_DIV,
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"lcd_pclk", CGU_CLK_DIV,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_LPCDR, 0, 11, -1, -1, -1 },
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.div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
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},
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},
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[JZ4740_CLK_I2S] = {
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[JZ4740_CLK_I2S] = {
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"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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"i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
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.mux = { CGU_REG_CPCCR, 31, 1 },
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.mux = { CGU_REG_CPCCR, 31, 1 },
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.div = { CGU_REG_I2SCDR, 0, 8, -1, -1, -1 },
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.div = { CGU_REG_I2SCDR, 0, 1, 8, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 6 },
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.gate = { CGU_REG_CLKGR, 6 },
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},
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},
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@ -142,21 +142,21 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
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"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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"spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
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.mux = { CGU_REG_SSICDR, 31, 1 },
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.mux = { CGU_REG_SSICDR, 31, 1 },
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.div = { CGU_REG_SSICDR, 0, 4, -1, -1, -1 },
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.div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 4 },
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.gate = { CGU_REG_CLKGR, 4 },
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},
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},
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[JZ4740_CLK_MMC] = {
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[JZ4740_CLK_MMC] = {
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"mmc", CGU_CLK_DIV | CGU_CLK_GATE,
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"mmc", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_MSCCDR, 0, 5, -1, -1, -1 },
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.div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 7 },
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.gate = { CGU_REG_CLKGR, 7 },
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},
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},
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[JZ4740_CLK_UHC] = {
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[JZ4740_CLK_UHC] = {
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"uhc", CGU_CLK_DIV | CGU_CLK_GATE,
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"uhc", CGU_CLK_DIV | CGU_CLK_GATE,
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
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.div = { CGU_REG_UHCCDR, 0, 4, -1, -1, -1 },
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.div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
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.gate = { CGU_REG_CLKGR, 14 },
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.gate = { CGU_REG_CLKGR, 14 },
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},
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},
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@ -164,7 +164,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
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"udc", CGU_CLK_MUX | CGU_CLK_DIV,
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"udc", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
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.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
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.mux = { CGU_REG_CPCCR, 29, 1 },
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.mux = { CGU_REG_CPCCR, 29, 1 },
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.div = { CGU_REG_CPCCR, 23, 6, -1, -1, -1 },
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.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
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.gate = { CGU_REG_SCR, 6 },
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.gate = { CGU_REG_SCR, 6 },
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},
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},
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@ -296,13 +296,13 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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[JZ4780_CLK_CPU] = {
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[JZ4780_CLK_CPU] = {
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"cpu", CGU_CLK_DIV,
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"cpu", CGU_CLK_DIV,
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.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
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.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 0, 4, 22, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 0, 1, 4, 22, -1, -1 },
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},
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},
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[JZ4780_CLK_L2CACHE] = {
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[JZ4780_CLK_L2CACHE] = {
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"l2cache", CGU_CLK_DIV,
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"l2cache", CGU_CLK_DIV,
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.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
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.parents = { JZ4780_CLK_CPUMUX, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 4, 4, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 4, 1, 4, -1, -1, -1 },
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},
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},
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[JZ4780_CLK_AHB0] = {
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[JZ4780_CLK_AHB0] = {
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@ -310,7 +310,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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JZ4780_CLK_EPLL },
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JZ4780_CLK_EPLL },
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.mux = { CGU_REG_CLOCKCONTROL, 26, 2 },
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.mux = { CGU_REG_CLOCKCONTROL, 26, 2 },
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.div = { CGU_REG_CLOCKCONTROL, 8, 4, 21, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 8, 1, 4, 21, -1, -1 },
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},
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},
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[JZ4780_CLK_AHB2PMUX] = {
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[JZ4780_CLK_AHB2PMUX] = {
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@ -323,20 +323,20 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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[JZ4780_CLK_AHB2] = {
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[JZ4780_CLK_AHB2] = {
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"ahb2", CGU_CLK_DIV,
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"ahb2", CGU_CLK_DIV,
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.parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
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.parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 12, 4, 20, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 12, 1, 4, 20, -1, -1 },
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},
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},
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[JZ4780_CLK_PCLK] = {
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[JZ4780_CLK_PCLK] = {
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"pclk", CGU_CLK_DIV,
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"pclk", CGU_CLK_DIV,
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.parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
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.parents = { JZ4780_CLK_AHB2PMUX, -1, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 16, 4, 20, -1, -1 },
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.div = { CGU_REG_CLOCKCONTROL, 16, 1, 4, 20, -1, -1 },
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},
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},
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[JZ4780_CLK_DDR] = {
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[JZ4780_CLK_DDR] = {
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"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
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"ddr", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
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.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1 },
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.mux = { CGU_REG_DDRCDR, 30, 2 },
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.mux = { CGU_REG_DDRCDR, 30, 2 },
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.div = { CGU_REG_DDRCDR, 0, 4, 29, 28, 27 },
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.div = { CGU_REG_DDRCDR, 0, 1, 4, 29, 28, 27 },
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},
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},
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[JZ4780_CLK_VPU] = {
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[JZ4780_CLK_VPU] = {
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@ -344,7 +344,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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JZ4780_CLK_EPLL, -1 },
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JZ4780_CLK_EPLL, -1 },
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.mux = { CGU_REG_VPUCDR, 30, 2 },
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.mux = { CGU_REG_VPUCDR, 30, 2 },
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.div = { CGU_REG_VPUCDR, 0, 4, 29, 28, 27 },
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.div = { CGU_REG_VPUCDR, 0, 1, 4, 29, 28, 27 },
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.gate = { CGU_REG_CLKGR1, 2 },
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.gate = { CGU_REG_CLKGR1, 2 },
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},
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},
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@ -352,7 +352,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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"i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
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"i2s_pll", CGU_CLK_MUX | CGU_CLK_DIV,
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_EPLL, -1, -1 },
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.mux = { CGU_REG_I2SCDR, 30, 1 },
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.mux = { CGU_REG_I2SCDR, 30, 1 },
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.div = { CGU_REG_I2SCDR, 0, 8, 29, 28, 27 },
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.div = { CGU_REG_I2SCDR, 0, 1, 8, 29, 28, 27 },
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},
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},
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[JZ4780_CLK_I2S] = {
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[JZ4780_CLK_I2S] = {
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@ -366,7 +366,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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JZ4780_CLK_VPLL, -1 },
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JZ4780_CLK_VPLL, -1 },
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.mux = { CGU_REG_LP0CDR, 30, 2 },
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.mux = { CGU_REG_LP0CDR, 30, 2 },
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.div = { CGU_REG_LP0CDR, 0, 8, 28, 27, 26 },
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.div = { CGU_REG_LP0CDR, 0, 1, 8, 28, 27, 26 },
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},
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},
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[JZ4780_CLK_LCD1PIXCLK] = {
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[JZ4780_CLK_LCD1PIXCLK] = {
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@ -374,7 +374,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
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.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||||
JZ4780_CLK_VPLL, -1 },
|
JZ4780_CLK_VPLL, -1 },
|
||||||
.mux = { CGU_REG_LP1CDR, 30, 2 },
|
.mux = { CGU_REG_LP1CDR, 30, 2 },
|
||||||
.div = { CGU_REG_LP1CDR, 0, 8, 28, 27, 26 },
|
.div = { CGU_REG_LP1CDR, 0, 1, 8, 28, 27, 26 },
|
||||||
},
|
},
|
||||||
|
|
||||||
[JZ4780_CLK_MSCMUX] = {
|
[JZ4780_CLK_MSCMUX] = {
|
||||||
|
@ -386,21 +386,21 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
||||||
[JZ4780_CLK_MSC0] = {
|
[JZ4780_CLK_MSC0] = {
|
||||||
"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
|
"msc0", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||||
.parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
|
.parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
|
||||||
.div = { CGU_REG_MSC0CDR, 0, 8, 29, 28, 27 },
|
.div = { CGU_REG_MSC0CDR, 0, 2, 8, 29, 28, 27 },
|
||||||
.gate = { CGU_REG_CLKGR0, 3 },
|
.gate = { CGU_REG_CLKGR0, 3 },
|
||||||
},
|
},
|
||||||
|
|
||||||
[JZ4780_CLK_MSC1] = {
|
[JZ4780_CLK_MSC1] = {
|
||||||
"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
|
"msc1", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||||
.parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
|
.parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
|
||||||
.div = { CGU_REG_MSC1CDR, 0, 8, 29, 28, 27 },
|
.div = { CGU_REG_MSC1CDR, 0, 2, 8, 29, 28, 27 },
|
||||||
.gate = { CGU_REG_CLKGR0, 11 },
|
.gate = { CGU_REG_CLKGR0, 11 },
|
||||||
},
|
},
|
||||||
|
|
||||||
[JZ4780_CLK_MSC2] = {
|
[JZ4780_CLK_MSC2] = {
|
||||||
"msc2", CGU_CLK_DIV | CGU_CLK_GATE,
|
"msc2", CGU_CLK_DIV | CGU_CLK_GATE,
|
||||||
.parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
|
.parents = { JZ4780_CLK_MSCMUX, -1, -1, -1 },
|
||||||
.div = { CGU_REG_MSC2CDR, 0, 8, 29, 28, 27 },
|
.div = { CGU_REG_MSC2CDR, 0, 2, 8, 29, 28, 27 },
|
||||||
.gate = { CGU_REG_CLKGR0, 12 },
|
.gate = { CGU_REG_CLKGR0, 12 },
|
||||||
},
|
},
|
||||||
|
|
||||||
|
@ -409,7 +409,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
||||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||||
JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY },
|
JZ4780_CLK_EPLL, JZ4780_CLK_OTGPHY },
|
||||||
.mux = { CGU_REG_UHCCDR, 30, 2 },
|
.mux = { CGU_REG_UHCCDR, 30, 2 },
|
||||||
.div = { CGU_REG_UHCCDR, 0, 8, 29, 28, 27 },
|
.div = { CGU_REG_UHCCDR, 0, 1, 8, 29, 28, 27 },
|
||||||
.gate = { CGU_REG_CLKGR0, 24 },
|
.gate = { CGU_REG_CLKGR0, 24 },
|
||||||
},
|
},
|
||||||
|
|
||||||
|
@ -417,7 +417,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
||||||
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
|
"ssi_pll", CGU_CLK_MUX | CGU_CLK_DIV,
|
||||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
|
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
|
||||||
.mux = { CGU_REG_SSICDR, 30, 1 },
|
.mux = { CGU_REG_SSICDR, 30, 1 },
|
||||||
.div = { CGU_REG_SSICDR, 0, 8, 29, 28, 27 },
|
.div = { CGU_REG_SSICDR, 0, 1, 8, 29, 28, 27 },
|
||||||
},
|
},
|
||||||
|
|
||||||
[JZ4780_CLK_SSI] = {
|
[JZ4780_CLK_SSI] = {
|
||||||
|
@ -430,7 +430,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
||||||
"cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV,
|
"cim_mclk", CGU_CLK_MUX | CGU_CLK_DIV,
|
||||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
|
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL, -1, -1 },
|
||||||
.mux = { CGU_REG_CIMCDR, 31, 1 },
|
.mux = { CGU_REG_CIMCDR, 31, 1 },
|
||||||
.div = { CGU_REG_CIMCDR, 0, 8, 30, 29, 28 },
|
.div = { CGU_REG_CIMCDR, 0, 1, 8, 30, 29, 28 },
|
||||||
},
|
},
|
||||||
|
|
||||||
[JZ4780_CLK_PCMPLL] = {
|
[JZ4780_CLK_PCMPLL] = {
|
||||||
|
@ -438,7 +438,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
||||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||||
JZ4780_CLK_EPLL, JZ4780_CLK_VPLL },
|
JZ4780_CLK_EPLL, JZ4780_CLK_VPLL },
|
||||||
.mux = { CGU_REG_PCMCDR, 29, 2 },
|
.mux = { CGU_REG_PCMCDR, 29, 2 },
|
||||||
.div = { CGU_REG_PCMCDR, 0, 8, 28, 27, 26 },
|
.div = { CGU_REG_PCMCDR, 0, 1, 8, 28, 27, 26 },
|
||||||
},
|
},
|
||||||
|
|
||||||
[JZ4780_CLK_PCM] = {
|
[JZ4780_CLK_PCM] = {
|
||||||
|
@ -453,7 +453,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
||||||
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||||
JZ4780_CLK_EPLL },
|
JZ4780_CLK_EPLL },
|
||||||
.mux = { CGU_REG_GPUCDR, 30, 2 },
|
.mux = { CGU_REG_GPUCDR, 30, 2 },
|
||||||
.div = { CGU_REG_GPUCDR, 0, 4, 29, 28, 27 },
|
.div = { CGU_REG_GPUCDR, 0, 1, 4, 29, 28, 27 },
|
||||||
.gate = { CGU_REG_CLKGR1, 4 },
|
.gate = { CGU_REG_CLKGR1, 4 },
|
||||||
},
|
},
|
||||||
|
|
||||||
|
@ -462,7 +462,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
||||||
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
.parents = { JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||||
JZ4780_CLK_VPLL, -1 },
|
JZ4780_CLK_VPLL, -1 },
|
||||||
.mux = { CGU_REG_HDMICDR, 30, 2 },
|
.mux = { CGU_REG_HDMICDR, 30, 2 },
|
||||||
.div = { CGU_REG_HDMICDR, 0, 8, 29, 28, 26 },
|
.div = { CGU_REG_HDMICDR, 0, 1, 8, 29, 28, 26 },
|
||||||
.gate = { CGU_REG_CLKGR1, 9 },
|
.gate = { CGU_REG_CLKGR1, 9 },
|
||||||
},
|
},
|
||||||
|
|
||||||
|
@ -471,7 +471,7 @@ static const struct ingenic_cgu_clk_info jz4780_cgu_clocks[] = {
|
||||||
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
.parents = { -1, JZ4780_CLK_SCLKA, JZ4780_CLK_MPLL,
|
||||||
JZ4780_CLK_EPLL },
|
JZ4780_CLK_EPLL },
|
||||||
.mux = { CGU_REG_BCHCDR, 30, 2 },
|
.mux = { CGU_REG_BCHCDR, 30, 2 },
|
||||||
.div = { CGU_REG_BCHCDR, 0, 4, 29, 28, 27 },
|
.div = { CGU_REG_BCHCDR, 0, 1, 4, 29, 28, 27 },
|
||||||
.gate = { CGU_REG_CLKGR0, 1 },
|
.gate = { CGU_REG_CLKGR0, 1 },
|
||||||
},
|
},
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue