arm64: KVM: Use SMCCC_ARCH_WORKAROUND_1 for Falkor BP hardening
The function SMCCC_ARCH_WORKAROUND_1 was introduced as part of SMC V1.1 Calling Convention to mitigate CVE-2017-5715. This patch uses the standard call SMCCC_ARCH_WORKAROUND_1 for Falkor chips instead of Silicon provider service ID 0xC2001700. Cc: <stable@vger.kernel.org> # 4.14+ Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org> [maz: reworked errata framework integration] Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -43,13 +43,12 @@
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#define ARM64_SVE 22
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#define ARM64_SVE 22
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#define ARM64_UNMAP_KERNEL_AT_EL0 23
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#define ARM64_UNMAP_KERNEL_AT_EL0 23
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#define ARM64_HARDEN_BRANCH_PREDICTOR 24
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#define ARM64_HARDEN_BRANCH_PREDICTOR 24
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#define ARM64_HARDEN_BP_POST_GUEST_EXIT 25
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#define ARM64_HAS_RAS_EXTN 25
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#define ARM64_HAS_RAS_EXTN 26
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#define ARM64_WORKAROUND_843419 26
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#define ARM64_WORKAROUND_843419 27
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#define ARM64_HAS_CACHE_IDC 27
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#define ARM64_HAS_CACHE_IDC 28
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#define ARM64_HAS_CACHE_DIC 28
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#define ARM64_HAS_CACHE_DIC 29
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#define ARM64_HW_DBM 29
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#define ARM64_HW_DBM 30
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#define ARM64_NCAPS 31
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#define ARM64_NCAPS 30
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#endif /* __ASM_CPUCAPS_H */
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#endif /* __ASM_CPUCAPS_H */
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@ -71,8 +71,6 @@ extern u32 __kvm_get_mdcr_el2(void);
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extern u32 __init_stage2_translation(void);
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extern u32 __init_stage2_translation(void);
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extern void __qcom_hyp_sanitize_btac_predictors(void);
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#else /* __ASSEMBLY__ */
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#else /* __ASSEMBLY__ */
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.macro get_host_ctxt reg, tmp
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.macro get_host_ctxt reg, tmp
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@ -74,14 +74,6 @@ ENTRY(__bp_harden_hyp_vecs_end)
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.popsection
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.popsection
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ENTRY(__qcom_hyp_sanitize_link_stack_start)
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stp x29, x30, [sp, #-16]!
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.rept 16
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bl . + 4
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.endr
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ldp x29, x30, [sp], #16
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ENTRY(__qcom_hyp_sanitize_link_stack_end)
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.macro smccc_workaround_1 inst
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.macro smccc_workaround_1 inst
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sub sp, sp, #(8 * 4)
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sub sp, sp, #(8 * 4)
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stp x2, x3, [sp, #(8 * 0)]
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stp x2, x3, [sp, #(8 * 0)]
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@ -87,8 +87,6 @@ atomic_t arm64_el2_vector_last_slot = ATOMIC_INIT(-1);
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DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data);
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#ifdef CONFIG_KVM
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#ifdef CONFIG_KVM
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extern char __qcom_hyp_sanitize_link_stack_start[];
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extern char __qcom_hyp_sanitize_link_stack_end[];
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extern char __smccc_workaround_1_smc_start[];
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extern char __smccc_workaround_1_smc_start[];
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extern char __smccc_workaround_1_smc_end[];
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extern char __smccc_workaround_1_smc_end[];
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extern char __smccc_workaround_1_hvc_start[];
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extern char __smccc_workaround_1_hvc_start[];
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@ -132,8 +130,6 @@ static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
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spin_unlock(&bp_lock);
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spin_unlock(&bp_lock);
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}
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}
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#else
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#else
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#define __qcom_hyp_sanitize_link_stack_start NULL
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#define __qcom_hyp_sanitize_link_stack_end NULL
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#define __smccc_workaround_1_smc_start NULL
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#define __smccc_workaround_1_smc_start NULL
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#define __smccc_workaround_1_smc_end NULL
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#define __smccc_workaround_1_smc_end NULL
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#define __smccc_workaround_1_hvc_start NULL
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#define __smccc_workaround_1_hvc_start NULL
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@ -178,12 +174,25 @@ static void call_hvc_arch_workaround_1(void)
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
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}
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}
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static void qcom_link_stack_sanitization(void)
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{
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u64 tmp;
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asm volatile("mov %0, x30 \n"
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".rept 16 \n"
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"bl . + 4 \n"
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".endr \n"
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"mov x30, %0 \n"
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: "=&r" (tmp));
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}
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static void
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static void
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enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
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enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
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{
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{
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bp_hardening_cb_t cb;
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bp_hardening_cb_t cb;
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void *smccc_start, *smccc_end;
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void *smccc_start, *smccc_end;
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struct arm_smccc_res res;
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struct arm_smccc_res res;
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u32 midr = read_cpuid_id();
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if (!entry->matches(entry, SCOPE_LOCAL_CPU))
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if (!entry->matches(entry, SCOPE_LOCAL_CPU))
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return;
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return;
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@ -216,30 +225,14 @@ enable_smccc_arch_workaround_1(const struct arm64_cpu_capabilities *entry)
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return;
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return;
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}
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}
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if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
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((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1))
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cb = qcom_link_stack_sanitization;
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install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
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install_bp_hardening_cb(entry, cb, smccc_start, smccc_end);
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return;
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return;
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}
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}
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static void qcom_link_stack_sanitization(void)
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{
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u64 tmp;
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asm volatile("mov %0, x30 \n"
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".rept 16 \n"
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"bl . + 4 \n"
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".endr \n"
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"mov x30, %0 \n"
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: "=&r" (tmp));
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}
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static void
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qcom_enable_link_stack_sanitization(const struct arm64_cpu_capabilities *entry)
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{
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install_bp_hardening_cb(entry, qcom_link_stack_sanitization,
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__qcom_hyp_sanitize_link_stack_start,
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__qcom_hyp_sanitize_link_stack_end);
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}
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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#endif /* CONFIG_HARDEN_BRANCH_PREDICTOR */
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#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
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#define CAP_MIDR_RANGE(model, v_min, r_min, v_max, r_max) \
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@ -324,27 +317,11 @@ static const struct midr_range arm64_bp_harden_smccc_cpus[] = {
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A75),
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
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MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
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{},
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};
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static const struct midr_range qcom_bp_harden_cpus[] = {
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR_V1),
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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MIDR_ALL_VERSIONS(MIDR_QCOM_FALKOR),
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{},
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{},
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};
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};
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static const struct arm64_cpu_capabilities arm64_bp_harden_list[] = {
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{
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CAP_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
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.cpu_enable = enable_smccc_arch_workaround_1,
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},
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{
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CAP_MIDR_RANGE_LIST(qcom_bp_harden_cpus),
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.cpu_enable = qcom_enable_link_stack_sanitization,
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},
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{},
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};
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#endif
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#endif
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#ifndef ERRATA_MIDR_ALL_VERSIONS
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#ifndef ERRATA_MIDR_ALL_VERSIONS
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@ -495,13 +472,8 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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{
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{
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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.capability = ARM64_HARDEN_BRANCH_PREDICTOR,
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
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.type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM,
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.matches = multi_entry_cap_matches,
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.cpu_enable = enable_smccc_arch_workaround_1,
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.cpu_enable = multi_entry_cap_cpu_enable,
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ERRATA_MIDR_RANGE_LIST(arm64_bp_harden_smccc_cpus),
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.match_list = arm64_bp_harden_list,
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},
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{
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.capability = ARM64_HARDEN_BP_POST_GUEST_EXIT,
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ERRATA_MIDR_RANGE_LIST(qcom_bp_harden_cpus),
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},
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},
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#endif
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#endif
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#ifdef CONFIG_HARDEN_EL2_VECTORS
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#ifdef CONFIG_HARDEN_EL2_VECTORS
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@ -209,15 +209,3 @@ alternative_endif
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eret
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eret
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ENDPROC(__fpsimd_guest_restore)
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ENDPROC(__fpsimd_guest_restore)
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ENTRY(__qcom_hyp_sanitize_btac_predictors)
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/**
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* Call SMC64 with Silicon provider serviceID 23<<8 (0xc2001700)
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* 0xC2000000-0xC200FFFF: assigned to SiP Service Calls
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* b15-b0: contains SiP functionID
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*/
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movz x0, #0x1700
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movk x0, #0xc200, lsl #16
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smc #0
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ret
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ENDPROC(__qcom_hyp_sanitize_btac_predictors)
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@ -472,16 +472,6 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
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/* And we're baaack! */
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/* And we're baaack! */
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} while (fixup_guest_exit(vcpu, &exit_code));
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} while (fixup_guest_exit(vcpu, &exit_code));
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if (cpus_have_const_cap(ARM64_HARDEN_BP_POST_GUEST_EXIT)) {
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u32 midr = read_cpuid_id();
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/* Apply BTAC predictors mitigation to all Falkor chips */
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if (((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR) ||
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((midr & MIDR_CPU_MODEL_MASK) == MIDR_QCOM_FALKOR_V1)) {
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__qcom_hyp_sanitize_btac_predictors();
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}
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}
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fp_enabled = __fpsimd_enabled_nvhe();
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fp_enabled = __fpsimd_enabled_nvhe();
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__sysreg_save_state_nvhe(guest_ctxt);
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__sysreg_save_state_nvhe(guest_ctxt);
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