sh: Add div6_reparent_clks to clock framework for FSI
Current clk_ops doesn't support .init which is used to select external clock on ecovec without CONFIG_SH_CLK_CPG_LEGACY. To solve this problem, this patch add div6_reparent_clks to clock-sh7724. This patch solve compile error too. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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@ -720,32 +720,6 @@ static struct platform_device camera_devices[] = {
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};
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};
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/* FSI */
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/* FSI */
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/*
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* FSI-B use external clock which came from da7210.
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* So, we should change parent of fsi
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*/
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#define FCLKBCR 0xa415000c
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static void fsimck_init(struct clk *clk)
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{
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u32 status = __raw_readl(clk->enable_reg);
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/* use external clock */
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status &= ~0x000000ff;
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status |= 0x00000080;
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__raw_writel(status, clk->enable_reg);
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}
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static struct clk_ops fsimck_clk_ops = {
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.init = fsimck_init,
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};
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static struct clk fsimckb_clk = {
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.ops = &fsimck_clk_ops,
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.enable_reg = (void __iomem *)FCLKBCR,
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.rate = 0, /* unknown */
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};
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static struct sh_fsi_platform_info fsi_info = {
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static struct sh_fsi_platform_info fsi_info = {
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.portb_flags = SH_FSI_BRS_INV |
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.portb_flags = SH_FSI_BRS_INV |
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SH_FSI_OUT_SLAVE_MODE |
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SH_FSI_OUT_SLAVE_MODE |
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@ -1264,10 +1238,10 @@ static int __init arch_setup(void)
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/* change parent of FSI B */
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/* change parent of FSI B */
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clk = clk_get(NULL, "fsib_clk");
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clk = clk_get(NULL, "fsib_clk");
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if (!IS_ERR(clk)) {
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if (!IS_ERR(clk)) {
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clk_register(&fsimckb_clk);
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/* 48kHz dummy clock was used to make sure 1/1 divide */
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clk_set_parent(clk, &fsimckb_clk);
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clk_set_rate(&sh7724_fsimckb_clk, 48000);
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clk_set_rate(clk, 11000);
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clk_set_parent(clk, &sh7724_fsimckb_clk);
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clk_set_rate(&fsimckb_clk, 11000);
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clk_set_rate(clk, 48000);
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clk_put(clk);
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clk_put(clk);
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}
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}
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@ -303,4 +303,7 @@ enum {
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SHDMA_SLAVE_SDHI1_RX,
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SHDMA_SLAVE_SDHI1_RX,
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};
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};
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extern struct clk sh7724_fsimcka_clk;
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extern struct clk sh7724_fsimckb_clk;
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#endif /* __ASM_SH7724_H__ */
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#endif /* __ASM_SH7724_H__ */
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@ -111,12 +111,21 @@ static struct clk div3_clk = {
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.parent = &pll_clk,
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.parent = &pll_clk,
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};
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};
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/* External input clock (pin name: FSIMCKA/FSIMCKB ) */
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struct clk sh7724_fsimcka_clk = {
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};
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struct clk sh7724_fsimckb_clk = {
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};
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static struct clk *main_clks[] = {
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static struct clk *main_clks[] = {
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&r_clk,
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&r_clk,
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&extal_clk,
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&extal_clk,
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&fll_clk,
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&fll_clk,
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&pll_clk,
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&pll_clk,
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&div3_clk,
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&div3_clk,
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&sh7724_fsimcka_clk,
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&sh7724_fsimckb_clk,
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};
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};
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static void div4_kick(struct clk *clk)
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static void div4_kick(struct clk *clk)
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@ -154,16 +163,38 @@ struct clk div4_clks[DIV4_NR] = {
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[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
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[DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
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};
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};
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enum { DIV6_V, DIV6_FA, DIV6_FB, DIV6_I, DIV6_S, DIV6_NR };
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enum { DIV6_V, DIV6_I, DIV6_S, DIV6_NR };
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static struct clk div6_clks[DIV6_NR] = {
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
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[DIV6_V] = SH_CLK_DIV6(&div3_clk, VCLKCR, 0),
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[DIV6_FA] = SH_CLK_DIV6(&div3_clk, FCLKACR, 0),
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[DIV6_FB] = SH_CLK_DIV6(&div3_clk, FCLKBCR, 0),
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[DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
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[DIV6_I] = SH_CLK_DIV6(&div3_clk, IRDACLKCR, 0),
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[DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
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[DIV6_S] = SH_CLK_DIV6(&div3_clk, SPUCLKCR, CLK_ENABLE_ON_INIT),
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};
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};
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enum { DIV6_FA, DIV6_FB, DIV6_REPARENT_NR };
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/* Indices are important - they are the actual src selecting values */
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static struct clk *fclkacr_parent[] = {
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[0] = &div3_clk,
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[1] = NULL,
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[2] = &sh7724_fsimcka_clk,
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[3] = NULL,
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};
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static struct clk *fclkbcr_parent[] = {
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[0] = &div3_clk,
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[1] = NULL,
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[2] = &sh7724_fsimckb_clk,
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[3] = NULL,
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};
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static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
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[DIV6_FA] = SH_CLK_DIV6_EXT(&div3_clk, FCLKACR, 0,
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fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2),
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[DIV6_FB] = SH_CLK_DIV6_EXT(&div3_clk, FCLKBCR, 0,
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fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2),
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};
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static struct clk mstp_clks[HWBLK_NR] = {
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static struct clk mstp_clks[HWBLK_NR] = {
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SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_TLB, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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SH_HWBLK_CLK(HWBLK_IC, &div4_clks[DIV4_I], CLK_ENABLE_ON_INIT),
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@ -240,8 +271,8 @@ static struct clk_lookup lookups[] = {
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/* DIV6 clocks */
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/* DIV6 clocks */
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CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
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CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
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CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]),
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CLKDEV_CON_ID("fsia_clk", &div6_reparent_clks[DIV6_FA]),
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CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]),
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CLKDEV_CON_ID("fsib_clk", &div6_reparent_clks[DIV6_FB]),
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CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
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CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]),
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CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
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CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]),
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@ -375,6 +406,9 @@ int __init arch_clk_init(void)
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if (!ret)
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if (!ret)
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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ret = sh_clk_div6_register(div6_clks, DIV6_NR);
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if (!ret)
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ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
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if (!ret)
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if (!ret)
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ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
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ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
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