parisc: Optimze cache flush algorithms
The attached patch implements three optimizations: 1) Loops in flush_user_dcache_range_asm, flush_kernel_dcache_range_asm, purge_kernel_dcache_range_asm, flush_user_icache_range_asm, and flush_kernel_icache_range_asm are unrolled to reduce branch overhead. 2) The static branch prediction for cmpb instructions in pacache.S have been reviewed and the operand order adjusted where necessary. 3) For flush routines in cache.c, we purge rather flush when we have no context. The pdc instruction at level 0 is not required to write back dirty lines to memory. This provides a performance improvement over the fdc instruction if the feature is implemented. Version 2 adds alternative patching. The patch provides an average improvement of about 2%. Signed-off-by: John David Anglin <dave.anglin@bell.net> Signed-off-by: Helge Deller <deller@gmx.de>
This commit is contained in:
parent
5a23237f14
commit
4c5fe5db1a
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@ -36,6 +36,7 @@ EXPORT_SYMBOL(dcache_stride);
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void flush_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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EXPORT_SYMBOL(flush_dcache_page_asm);
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void purge_dcache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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void flush_icache_page_asm(unsigned long phys_addr, unsigned long vaddr);
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@ -303,6 +304,17 @@ __flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
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preempt_enable();
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}
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static inline void
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__purge_cache_page(struct vm_area_struct *vma, unsigned long vmaddr,
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unsigned long physaddr)
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{
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preempt_disable();
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purge_dcache_page_asm(physaddr, vmaddr);
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if (vma->vm_flags & VM_EXEC)
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flush_icache_page_asm(physaddr, vmaddr);
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preempt_enable();
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}
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void flush_dcache_page(struct page *page)
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{
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struct address_space *mapping = page_mapping_file(page);
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@ -563,9 +575,12 @@ void flush_cache_mm(struct mm_struct *mm)
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pfn = pte_pfn(*ptep);
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if (!pfn_valid(pfn))
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continue;
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if (unlikely(mm->context))
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if (unlikely(mm->context)) {
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flush_tlb_page(vma, addr);
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__flush_cache_page(vma, addr, PFN_PHYS(pfn));
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} else {
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__purge_cache_page(vma, addr, PFN_PHYS(pfn));
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}
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}
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}
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}
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@ -600,9 +615,12 @@ void flush_cache_range(struct vm_area_struct *vma,
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continue;
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pfn = pte_pfn(*ptep);
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if (pfn_valid(pfn)) {
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if (unlikely(vma->vm_mm->context))
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if (unlikely(vma->vm_mm->context)) {
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flush_tlb_page(vma, addr);
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__flush_cache_page(vma, addr, PFN_PHYS(pfn));
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} else {
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__purge_cache_page(vma, addr, PFN_PHYS(pfn));
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}
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}
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}
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}
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@ -611,9 +629,12 @@ void
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flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long pfn)
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{
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if (pfn_valid(pfn)) {
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if (likely(vma->vm_mm->context))
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if (likely(vma->vm_mm->context)) {
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flush_tlb_page(vma, vmaddr);
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__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
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} else {
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__purge_cache_page(vma, vmaddr, PFN_PHYS(pfn));
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}
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}
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}
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@ -838,7 +838,6 @@ ENTRY_CFI(flush_dcache_page_asm)
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add %r28, %r25, %r25
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sub %r25, r31, %r25
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1: fdc,m r31(%r28)
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fdc,m r31(%r28)
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fdc,m r31(%r28)
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@ -854,7 +853,7 @@ ENTRY_CFI(flush_dcache_page_asm)
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fdc,m r31(%r28)
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fdc,m r31(%r28)
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fdc,m r31(%r28)
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cmpb,COND(<<) %r28, %r25,1b
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cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
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fdc,m r31(%r28)
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
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@ -863,6 +862,67 @@ ENTRY_CFI(flush_dcache_page_asm)
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nop
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ENDPROC_CFI(flush_dcache_page_asm)
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ENTRY_CFI(purge_dcache_page_asm)
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ldil L%(TMPALIAS_MAP_START), %r28
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#ifdef CONFIG_64BIT
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#if (TMPALIAS_MAP_START >= 0x80000000)
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depdi 0, 31,32, %r28 /* clear any sign extension */
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#endif
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convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
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depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
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depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
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#else
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extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
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depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
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depwi 0, 31,PAGE_SHIFT, %r28 /* Clear any offset bits */
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#endif
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/* Purge any old translation */
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#ifdef CONFIG_PA20
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pdtlb,l %r0(%r28)
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#else
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tlb_lock %r20,%r21,%r22
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0: pdtlb %r0(%r28)
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tlb_unlock %r20,%r21,%r22
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ALTERNATIVE(0b, 0b+4, ALT_COND_NO_SMP, INSN_PxTLB)
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#endif
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88: ldil L%dcache_stride, %r1
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ldw R%dcache_stride(%r1), r31
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#ifdef CONFIG_64BIT
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depdi,z 1, 63-PAGE_SHIFT,1, %r25
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#else
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depwi,z 1, 31-PAGE_SHIFT,1, %r25
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#endif
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add %r28, %r25, %r25
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sub %r25, r31, %r25
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1: pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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pdc,m r31(%r28)
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cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
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pdc,m r31(%r28)
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
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sync
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bv %r0(%r2)
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nop
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ENDPROC_CFI(purge_dcache_page_asm)
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ENTRY_CFI(flush_icache_page_asm)
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ldil L%(TMPALIAS_MAP_START), %r28
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#ifdef CONFIG_64BIT
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@ -908,7 +968,6 @@ ENTRY_CFI(flush_icache_page_asm)
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add %r28, %r25, %r25
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sub %r25, %r31, %r25
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/* fic only has the type 26 form on PA1.1, requiring an
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* explicit space specification, so use %sr4 */
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1: fic,m %r31(%sr4,%r28)
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@ -926,7 +985,7 @@ ENTRY_CFI(flush_icache_page_asm)
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fic,m %r31(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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fic,m %r31(%sr4,%r28)
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cmpb,COND(<<) %r28, %r25,1b
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cmpb,COND(>>) %r25, %r28, 1b /* predict taken */
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fic,m %r31(%sr4,%r28)
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
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@ -947,7 +1006,6 @@ ENTRY_CFI(flush_kernel_dcache_page_asm)
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add %r26, %r25, %r25
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sub %r25, %r23, %r25
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1: fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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@ -963,7 +1021,7 @@ ENTRY_CFI(flush_kernel_dcache_page_asm)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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cmpb,COND(<<) %r26, %r25,1b
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cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
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fdc,m %r23(%r26)
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
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@ -999,7 +1057,7 @@ ENTRY_CFI(purge_kernel_dcache_page_asm)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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cmpb,COND(<<) %r26, %r25, 1b
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cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
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pdc,m %r23(%r26)
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
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@ -1014,7 +1072,33 @@ ENTRY_CFI(flush_user_dcache_range_asm)
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ldo -1(%r23), %r21
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ANDCM %r26, %r21, %r26
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1: cmpb,COND(<<),n %r26, %r25, 1b
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#ifdef CONFIG_64BIT
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depd,z %r23, 59, 60, %r21
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#else
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depw,z %r23, 27, 28, %r21
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#endif
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add %r26, %r21, %r22
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
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1: add %r22, %r21, %r22
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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fdc,m %r23(%sr3, %r26)
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
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fdc,m %r23(%sr3, %r26)
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2: cmpb,COND(>>),n %r25, %r26, 2b
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fdc,m %r23(%sr3, %r26)
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_DCACHE, INSN_NOP)
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ldo -1(%r23), %r21
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ANDCM %r26, %r21, %r26
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1: cmpb,COND(<<),n %r26, %r25,1b
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#ifdef CONFIG_64BIT
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depd,z %r23, 59, 60, %r21
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#else
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depw,z %r23, 27, 28, %r21
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#endif
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add %r26, %r21, %r22
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
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1: add %r22, %r21, %r22
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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fdc,m %r23(%r26)
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
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fdc,m %r23(%r26)
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2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
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fdc,m %r23(%r26)
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sync
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@ -1045,7 +1155,33 @@ ENTRY_CFI(purge_kernel_dcache_range_asm)
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ldo -1(%r23), %r21
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ANDCM %r26, %r21, %r26
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1: cmpb,COND(<<),n %r26, %r25,1b
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#ifdef CONFIG_64BIT
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depd,z %r23, 59, 60, %r21
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#else
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depw,z %r23, 27, 28, %r21
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#endif
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add %r26, %r21, %r22
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
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1: add %r22, %r21, %r22
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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pdc,m %r23(%r26)
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
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pdc,m %r23(%r26)
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2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
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pdc,m %r23(%r26)
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sync
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@ -1061,7 +1197,33 @@ ENTRY_CFI(flush_user_icache_range_asm)
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ldo -1(%r23), %r21
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ANDCM %r26, %r21, %r26
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1: cmpb,COND(<<),n %r26, %r25,1b
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#ifdef CONFIG_64BIT
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depd,z %r23, 59, 60, %r21
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#else
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depw,z %r23, 27, 28, %r21
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#endif
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add %r26, %r21, %r22
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
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1: add %r22, %r21, %r22
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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fic,m %r23(%sr3, %r26)
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
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fic,m %r23(%sr3, %r26)
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2: cmpb,COND(>>),n %r25, %r26, 2b
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fic,m %r23(%sr3, %r26)
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
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@ -1098,7 +1260,7 @@ ENTRY_CFI(flush_kernel_icache_page)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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cmpb,COND(<<) %r26, %r25, 1b
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cmpb,COND(>>) %r25, %r26, 1b /* predict taken */
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fic,m %r23(%sr4, %r26)
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
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@ -1113,7 +1275,33 @@ ENTRY_CFI(flush_kernel_icache_range_asm)
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ldo -1(%r23), %r21
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ANDCM %r26, %r21, %r26
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1: cmpb,COND(<<),n %r26, %r25, 1b
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#ifdef CONFIG_64BIT
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depd,z %r23, 59, 60, %r21
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#else
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depw,z %r23, 27, 28, %r21
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#endif
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add %r26, %r21, %r22
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cmpb,COND(>>),n %r22, %r25, 2f /* predict not taken */
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1: add %r22, %r21, %r22
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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fic,m %r23(%sr4, %r26)
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cmpb,COND(<<=) %r22, %r25, 1b /* predict taken */
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fic,m %r23(%sr4, %r26)
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2: cmpb,COND(>>),n %r25, %r26, 2b /* predict taken */
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fic,m %r23(%sr4, %r26)
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89: ALTERNATIVE(88b, 89b, ALT_COND_NO_ICACHE, INSN_NOP)
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Reference in New Issue