Merge branch 'clk-cp110' of git://git.infradead.org/linux-mvebu into clk-next
Pull improved Marvel Armada 7K/8K cp110 clk support from Gregory CLEMENT: We got more information about the clock controllers and the clock tree of the CP110 part that we find in the Marvell Armada 7K/8K SoCs. The clk driver is modified accordingly from this new information. * 'clk-cp110' of git://git.infradead.org/linux-mvebu: clk: mvebu: cp110: add sdio clock to cp-110 system controller clk: mvebu: cp110: introduce a new binding clk: mvebu: cp110: do not depend anymore of the *-clock-output-names clk: mvebu: cp110: make failure labels more meaningful
This commit is contained in:
Stephen Boyd
commit
4d4f9a6a19
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@ -11,15 +11,16 @@
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*/
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/*
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* CP110 has 5 core clocks:
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* CP110 has 6 core clocks:
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*
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* - APLL (1 Ghz)
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* - PPv2 core (1/3 APLL)
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* - EIP (1/2 APLL)
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* - Core (1/2 EIP)
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* - Core (1/2 EIP)
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* - SDIO (2/5 APLL)
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*
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* - NAND clock, which is either:
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* - Equal to the core clock
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* - Equal to SDIO clock
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* - 2/5 APLL
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*
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* CP110 has 32 gatable clocks, for the various peripherals in the
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@ -46,7 +47,7 @@ enum {
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CP110_CLK_TYPE_GATABLE,
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};
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#define CP110_MAX_CORE_CLOCKS 5
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#define CP110_MAX_CORE_CLOCKS 6
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#define CP110_MAX_GATABLE_CLOCKS 32
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#define CP110_CLK_NUM \
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@ -57,6 +58,7 @@ enum {
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#define CP110_CORE_EIP 2
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#define CP110_CORE_CORE 3
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#define CP110_CORE_NAND 4
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#define CP110_CORE_SDIO 5
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/* A number of gatable clocks need special handling */
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#define CP110_GATE_AUDIO 0
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@ -84,6 +86,33 @@ enum {
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#define CP110_GATE_EIP150 25
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#define CP110_GATE_EIP197 26
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const char *gate_base_names[] = {
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[CP110_GATE_AUDIO] = "audio",
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[CP110_GATE_COMM_UNIT] = "communit",
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[CP110_GATE_NAND] = "nand",
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[CP110_GATE_PPV2] = "ppv2",
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[CP110_GATE_SDIO] = "sdio",
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[CP110_GATE_MG] = "mg-domain",
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[CP110_GATE_MG_CORE] = "mg-core",
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[CP110_GATE_XOR1] = "xor1",
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[CP110_GATE_XOR0] = "xor0",
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[CP110_GATE_GOP_DP] = "gop-dp",
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[CP110_GATE_PCIE_X1_0] = "pcie_x10",
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[CP110_GATE_PCIE_X1_1] = "pcie_x11",
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[CP110_GATE_PCIE_X4] = "pcie_x4",
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[CP110_GATE_PCIE_XOR] = "pcie-xor",
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[CP110_GATE_SATA] = "sata",
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[CP110_GATE_SATA_USB] = "sata-usb",
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[CP110_GATE_MAIN] = "main",
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[CP110_GATE_SDMMC_GOP] = "sd-mmc-gop",
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[CP110_GATE_SLOW_IO] = "slow-io",
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[CP110_GATE_USB3H0] = "usb3h0",
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[CP110_GATE_USB3H1] = "usb3h1",
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[CP110_GATE_USB3DEV] = "usb3dev",
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[CP110_GATE_EIP150] = "eip150",
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[CP110_GATE_EIP197] = "eip197"
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};
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struct cp110_gate_clk {
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struct clk_hw hw;
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struct regmap *regmap;
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@ -186,17 +215,37 @@ static struct clk_hw *cp110_of_clk_get(struct of_phandle_args *clkspec,
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return ERR_PTR(-EINVAL);
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}
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static int cp110_syscon_clk_probe(struct platform_device *pdev)
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static char *cp110_unique_name(struct device *dev, struct device_node *np,
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const char *name)
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{
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const __be32 *reg;
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u64 addr;
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/* Do not create a name if there is no clock */
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if (!name)
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return NULL;
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reg = of_get_property(np, "reg", NULL);
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addr = of_translate_address(np, reg);
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return devm_kasprintf(dev, GFP_KERNEL, "%llx-%s",
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(unsigned long long)addr, name);
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}
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static int cp110_syscon_common_probe(struct platform_device *pdev,
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struct device_node *syscon_node)
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{
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struct regmap *regmap;
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struct device_node *np = pdev->dev.of_node;
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const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name;
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struct device *dev = &pdev->dev;
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struct device_node *np = dev->of_node;
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const char *ppv2_name, *apll_name, *core_name, *eip_name, *nand_name,
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*sdio_name;
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struct clk_hw_onecell_data *cp110_clk_data;
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struct clk_hw *hw, **cp110_clks;
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u32 nand_clk_ctrl;
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int i, ret;
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char *gate_name[ARRAY_SIZE(gate_base_names)];
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regmap = syscon_node_to_regmap(np);
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regmap = syscon_node_to_regmap(syscon_node);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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@ -205,7 +254,7 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
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if (ret)
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return ret;
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cp110_clk_data = devm_kzalloc(&pdev->dev, sizeof(*cp110_clk_data) +
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cp110_clk_data = devm_kzalloc(dev, sizeof(*cp110_clk_data) +
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sizeof(struct clk_hw *) * CP110_CLK_NUM,
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GFP_KERNEL);
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if (!cp110_clk_data)
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@ -215,53 +264,47 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
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cp110_clk_data->num = CP110_CLK_NUM;
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/* Register the APLL which is the root of the hw tree */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_APLL, &apll_name);
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apll_name = cp110_unique_name(dev, syscon_node, "apll");
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hw = clk_hw_register_fixed_rate(NULL, apll_name, NULL, 0,
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1000 * 1000 * 1000);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail0;
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goto fail_apll;
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}
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cp110_clks[CP110_CORE_APLL] = hw;
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/* PPv2 is APLL/3 */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_PPV2, &ppv2_name);
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ppv2_name = cp110_unique_name(dev, syscon_node, "ppv2-core");
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hw = clk_hw_register_fixed_factor(NULL, ppv2_name, apll_name, 0, 1, 3);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail1;
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goto fail_ppv2;
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}
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cp110_clks[CP110_CORE_PPV2] = hw;
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/* EIP clock is APLL/2 */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_EIP, &eip_name);
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eip_name = cp110_unique_name(dev, syscon_node, "eip");
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hw = clk_hw_register_fixed_factor(NULL, eip_name, apll_name, 0, 1, 2);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail2;
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goto fail_eip;
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}
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cp110_clks[CP110_CORE_EIP] = hw;
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/* Core clock is EIP/2 */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_CORE, &core_name);
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core_name = cp110_unique_name(dev, syscon_node, "core");
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hw = clk_hw_register_fixed_factor(NULL, core_name, eip_name, 0, 1, 2);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail3;
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goto fail_core;
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}
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cp110_clks[CP110_CORE_CORE] = hw;
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/* NAND can be either APLL/2.5 or core clock */
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of_property_read_string_index(np, "core-clock-output-names",
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CP110_CORE_NAND, &nand_name);
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nand_name = cp110_unique_name(dev, syscon_node, "nand-core");
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if (nand_clk_ctrl & NF_CLOCK_SEL_400_MASK)
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hw = clk_hw_register_fixed_factor(NULL, nand_name,
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apll_name, 0, 2, 5);
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@ -270,23 +313,31 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
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core_name, 0, 1, 1);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail4;
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goto fail_nand;
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}
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cp110_clks[CP110_CORE_NAND] = hw;
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for (i = 0; i < CP110_MAX_GATABLE_CLOCKS; i++) {
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const char *parent, *name;
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int ret;
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/* SDIO clock is APLL/2.5 */
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sdio_name = cp110_unique_name(dev, syscon_node, "sdio-core");
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hw = clk_hw_register_fixed_factor(NULL, sdio_name,
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apll_name, 0, 2, 5);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail_sdio;
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}
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ret = of_property_read_string_index(np,
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"gate-clock-output-names",
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i, &name);
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/* Reached the end of the list? */
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if (ret < 0)
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break;
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cp110_clks[CP110_CORE_SDIO] = hw;
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if (!strcmp(name, "none"))
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/* create the unique name for all the gate clocks */
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for (i = 0; i < ARRAY_SIZE(gate_base_names); i++)
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gate_name[i] = cp110_unique_name(dev, syscon_node,
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gate_base_names[i]);
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for (i = 0; i < ARRAY_SIZE(gate_base_names); i++) {
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const char *parent;
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if (gate_name[i] == NULL)
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continue;
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switch (i) {
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@ -295,14 +346,10 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
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case CP110_GATE_EIP150:
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case CP110_GATE_EIP197:
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case CP110_GATE_SLOW_IO:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_MAIN, &parent);
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parent = gate_name[CP110_GATE_MAIN];
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break;
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case CP110_GATE_MG:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_MG_CORE, &parent);
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parent = gate_name[CP110_GATE_MG_CORE];
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break;
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case CP110_GATE_NAND:
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parent = nand_name;
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@ -311,34 +358,30 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
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parent = ppv2_name;
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break;
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case CP110_GATE_SDIO:
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parent = sdio_name;
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break;
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case CP110_GATE_GOP_DP:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_SDMMC_GOP, &parent);
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parent = gate_name[CP110_GATE_SDMMC_GOP];
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break;
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case CP110_GATE_XOR1:
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case CP110_GATE_XOR0:
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case CP110_GATE_PCIE_X1_0:
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case CP110_GATE_PCIE_X1_1:
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case CP110_GATE_PCIE_X4:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_PCIE_XOR, &parent);
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parent = gate_name[CP110_GATE_PCIE_XOR];
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break;
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case CP110_GATE_SATA:
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case CP110_GATE_USB3H0:
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case CP110_GATE_USB3H1:
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case CP110_GATE_USB3DEV:
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of_property_read_string_index(np,
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"gate-clock-output-names",
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CP110_GATE_SATA_USB, &parent);
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parent = gate_name[CP110_GATE_SATA_USB];
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break;
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default:
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parent = core_name;
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break;
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}
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hw = cp110_register_gate(gate_name[i], parent, regmap, i);
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hw = cp110_register_gate(name, parent, regmap, i);
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if (IS_ERR(hw)) {
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ret = PTR_ERR(hw);
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goto fail_gate;
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@ -364,30 +407,63 @@ fail_gate:
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cp110_unregister_gate(hw);
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}
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_SDIO]);
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fail_sdio:
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_NAND]);
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fail4:
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fail_nand:
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_CORE]);
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fail3:
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fail_core:
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_EIP]);
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fail2:
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fail_eip:
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clk_hw_unregister_fixed_factor(cp110_clks[CP110_CORE_PPV2]);
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fail1:
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fail_ppv2:
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clk_hw_unregister_fixed_rate(cp110_clks[CP110_CORE_APLL]);
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fail0:
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fail_apll:
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return ret;
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}
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static const struct of_device_id cp110_syscon_of_match[] = {
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static int cp110_syscon_legacy_clk_probe(struct platform_device *pdev)
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{
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dev_warn(&pdev->dev, FW_WARN "Using legacy device tree binding\n");
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dev_warn(&pdev->dev, FW_WARN "Update your device tree:\n");
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dev_warn(&pdev->dev, FW_WARN
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"This binding won't be supported in future kernels\n");
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return cp110_syscon_common_probe(pdev, pdev->dev.of_node);
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}
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static int cp110_clk_probe(struct platform_device *pdev)
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{
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return cp110_syscon_common_probe(pdev, pdev->dev.of_node->parent);
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}
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static const struct of_device_id cp110_syscon_legacy_of_match[] = {
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{ .compatible = "marvell,cp110-system-controller0", },
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{ }
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};
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static struct platform_driver cp110_syscon_driver = {
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.probe = cp110_syscon_clk_probe,
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static struct platform_driver cp110_syscon_legacy_driver = {
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.probe = *cp110_syscon_legacy_clk_probe,
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.driver = {
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.name = "marvell-cp110-system-controller0",
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.of_match_table = cp110_syscon_of_match,
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.of_match_table = cp110_syscon_legacy_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(cp110_syscon_driver);
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builtin_platform_driver(cp110_syscon_legacy_driver);
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static const struct of_device_id cp110_clock_of_match[] = {
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{ .compatible = "marvell,cp110-clock", },
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{ }
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};
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static struct platform_driver cp110_clock_driver = {
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.probe = cp110_clk_probe,
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.driver = {
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.name = "marvell-cp110-clock",
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.of_match_table = cp110_clock_of_match,
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.suppress_bind_attrs = true,
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},
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};
|
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builtin_platform_driver(cp110_clock_driver);
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|
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|
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