sb_edac: add support for Ivy Bridge
Since Ivy Bridge memory controller is very similar to Sandy Bridge, it's wiser to modify sb_edac to support both instead of creating another driver. [m.chehab@samsung.com: Fix CodingStyle] Signed-off-by: Aristeu Rozanski <arozansk@redhat.com> Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
This commit is contained in:
Aristeu Rozanski
Mauro Carvalho Chehab
parent
be3036d220
commit
4d715a805b
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@ -34,7 +34,7 @@ static int probed;
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/*
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* Alter this version for the module when modifications are made
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*/
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#define SBRIDGE_REVISION " Ver: 1.0.0 "
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#define SBRIDGE_REVISION " Ver: 1.1.0 "
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#define EDAC_MOD_STR "sbridge_edac"
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/*
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@ -88,6 +88,13 @@ static const u32 sbridge_dram_rule[] = {
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0xa8, 0xb0, 0xb8, 0xc0, 0xc8,
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};
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static const u32 ibridge_dram_rule[] = {
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0x60, 0x68, 0x70, 0x78, 0x80,
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0x88, 0x90, 0x98, 0xa0, 0xa8,
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0xb0, 0xb8, 0xc0, 0xc8, 0xd0,
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0xd8, 0xe0, 0xe8, 0xf0, 0xf8,
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};
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#define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff)
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#define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3)
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#define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1)
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@ -112,6 +119,13 @@ static const u32 sbridge_interleave_list[] = {
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0xac, 0xb4, 0xbc, 0xc4, 0xcc,
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};
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static const u32 ibridge_interleave_list[] = {
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0x64, 0x6c, 0x74, 0x7c, 0x84,
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0x8c, 0x94, 0x9c, 0xa4, 0xac,
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0xb4, 0xbc, 0xc4, 0xcc, 0xd4,
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0xdc, 0xe4, 0xec, 0xf4, 0xfc,
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};
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struct interleave_pkg {
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unsigned char start;
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unsigned char end;
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@ -128,6 +142,17 @@ static const struct interleave_pkg sbridge_interleave_pkg[] = {
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{ 27, 29 },
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};
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static const struct interleave_pkg ibridge_interleave_pkg[] = {
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{ 0, 3 },
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{ 4, 7 },
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{ 8, 11 },
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{ 12, 15 },
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{ 16, 19 },
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{ 20, 23 },
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{ 24, 27 },
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{ 28, 31 },
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};
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static inline int sad_pkg(const struct interleave_pkg *table, u32 reg,
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int interleave)
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{
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@ -252,6 +277,8 @@ static const u32 correrrthrsld[] = {
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#define SB_RANK_CFG_A 0x0328
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#define IB_RANK_CFG_A 0x0320
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#define IS_RDIMM_ENABLED(reg) GET_BITFIELD(reg, 11, 11)
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/*
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@ -261,8 +288,14 @@ static const u32 correrrthrsld[] = {
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#define NUM_CHANNELS 4
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#define MAX_DIMMS 3 /* Max DIMMS per channel */
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enum type {
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SANDY_BRIDGE,
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IVY_BRIDGE,
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};
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struct sbridge_pvt;
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struct sbridge_info {
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enum type type;
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u32 mcmtr;
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u32 rankcfgr;
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u64 (*get_tolm)(struct sbridge_pvt *pvt);
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@ -302,8 +335,9 @@ struct sbridge_dev {
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struct sbridge_pvt {
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struct pci_dev *pci_ta, *pci_ddrio, *pci_ras;
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struct pci_dev *pci_sad0, *pci_sad1, *pci_ha0;
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struct pci_dev *pci_br0;
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struct pci_dev *pci_sad0, *pci_sad1;
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struct pci_dev *pci_ha0, *pci_ha1;
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struct pci_dev *pci_br0, *pci_br1;
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struct pci_dev *pci_tad[NUM_CHANNELS];
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struct sbridge_dev *sbridge_dev;
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@ -361,11 +395,75 @@ static const struct pci_id_table pci_dev_descr_sbridge_table[] = {
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{0,} /* 0 terminated list. */
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};
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/* This changes depending if 1HA or 2HA:
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* 1HA:
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* 0x0eb8 (17.0) is DDRIO0
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* 2HA:
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* 0x0ebc (17.4) is DDRIO0
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*/
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0 0x0eb8
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0 0x0ebc
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/* pci ids */
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0 0x0ea0
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA 0x0ea8
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS 0x0e71
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0 0x0eaa
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1 0x0eab
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2 0x0eac
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3 0x0ead
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_SAD 0x0ec8
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_BR0 0x0ec9
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_BR1 0x0eca
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1 0x0e60
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA 0x0e68
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS 0x0e79
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0 0x0e6a
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#define PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1 0x0e6b
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static const struct pci_id_descr pci_dev_descr_ibridge[] = {
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/* Processor Home Agent */
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{ PCI_DESCR(14, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0, 0) },
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/* Memory controller */
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{ PCI_DESCR(15, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA, 0) },
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{ PCI_DESCR(15, 1, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_RAS, 0) },
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{ PCI_DESCR(15, 2, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD0, 0) },
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{ PCI_DESCR(15, 3, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD1, 0) },
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{ PCI_DESCR(15, 4, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD2, 0) },
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{ PCI_DESCR(15, 5, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TAD3, 0) },
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/* System Address Decoder */
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{ PCI_DESCR(22, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_SAD, 0) },
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/* Broadcast Registers */
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{ PCI_DESCR(22, 1, PCI_DEVICE_ID_INTEL_IBRIDGE_BR0, 1) },
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{ PCI_DESCR(22, 2, PCI_DEVICE_ID_INTEL_IBRIDGE_BR1, 0) },
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/* Optional, mode 2HA */
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{ PCI_DESCR(28, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, 1) },
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#if 0
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{ PCI_DESCR(29, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TA, 1) },
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{ PCI_DESCR(29, 1, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_RAS, 1) },
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#endif
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{ PCI_DESCR(29, 2, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD0, 1) },
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{ PCI_DESCR(29, 3, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1_TAD1, 1) },
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{ PCI_DESCR(17, 0, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_1HA_DDRIO0, 1) },
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{ PCI_DESCR(17, 4, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_2HA_DDRIO0, 1) },
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};
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static const struct pci_id_table pci_dev_descr_ibridge_table[] = {
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PCI_ID_TABLE_ENTRY(pci_dev_descr_ibridge),
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{0,} /* 0 terminated list. */
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};
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/*
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* pci_device_id table for which devices we are looking for
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*/
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static DEFINE_PCI_DEVICE_TABLE(sbridge_pci_tbl) = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TA)},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA)},
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{0,} /* 0 terminated list. */
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};
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@ -472,6 +570,35 @@ static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
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return GET_TOHM(reg);
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}
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static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
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{
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u32 reg;
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pci_read_config_dword(pvt->pci_br1, TOLM, ®);
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return GET_TOLM(reg);
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}
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static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
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{
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u32 reg;
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pci_read_config_dword(pvt->pci_br1, TOHM, ®);
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return GET_TOHM(reg);
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}
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static inline u8 sad_pkg_socket(u8 pkg)
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{
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/* on Ivy Bridge, nodeID is SASS, where A is HA and S is node id */
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return (pkg >> 3) | (pkg & 0x3);
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}
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static inline u8 sad_pkg_ha(u8 pkg)
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{
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return (pkg >> 2) & 0x1;
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}
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/****************************************************************************
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Memory check routines
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****************************************************************************/
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@ -534,8 +661,6 @@ static int get_dimm_config(struct mem_ctl_info *mci)
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enum edac_type mode;
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enum mem_type mtype;
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pvt->info.rankcfgr = SB_RANK_CFG_A;
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pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®);
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pvt->sbridge_dev->source_id = SOURCE_ID(reg);
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@ -810,12 +935,13 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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{
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struct mem_ctl_info *new_mci;
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struct sbridge_pvt *pvt = mci->pvt_info;
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struct pci_dev *pci_ha;
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int n_rir, n_sads, n_tads, sad_way, sck_xch;
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int sad_interl, idx, base_ch;
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int interleave_mode;
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unsigned sad_interleave[pvt->info.max_interleave];
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u32 reg;
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u8 ch_way,sck_way;
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u8 ch_way, sck_way, pkg, sad_ha = 0;
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u32 tad_offset;
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u32 rir_way;
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u32 mb, kb;
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@ -866,45 +992,56 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
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®);
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sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
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for (sad_way = 0; sad_way < 8; sad_way++) {
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u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
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if (sad_way > 0 && sad_interl == pkg)
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if (pvt->info.type == SANDY_BRIDGE) {
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sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
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for (sad_way = 0; sad_way < 8; sad_way++) {
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u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
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if (sad_way > 0 && sad_interl == pkg)
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break;
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sad_interleave[sad_way] = pkg;
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edac_dbg(0, "SAD interleave #%d: %d\n",
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sad_way, sad_interleave[sad_way]);
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}
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edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
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pvt->sbridge_dev->mc,
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n_sads,
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addr,
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limit,
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sad_way + 7,
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!interleave_mode ? "" : "XOR[18:16]");
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if (interleave_mode)
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idx = ((addr >> 6) ^ (addr >> 16)) & 7;
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else
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idx = (addr >> 6) & 7;
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switch (sad_way) {
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case 1:
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idx = 0;
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break;
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sad_interleave[sad_way] = pkg;
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edac_dbg(0, "SAD interleave #%d: %d\n",
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sad_way, sad_interleave[sad_way]);
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}
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edac_dbg(0, "mc#%d: Error detected on SAD#%d: address 0x%016Lx < 0x%016Lx, Interleave [%d:6]%s\n",
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pvt->sbridge_dev->mc,
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n_sads,
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addr,
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limit,
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sad_way + 7,
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interleave_mode ? "" : "XOR[18:16]");
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if (interleave_mode)
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idx = ((addr >> 6) ^ (addr >> 16)) & 7;
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else
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case 2:
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idx = idx & 1;
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break;
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case 4:
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idx = idx & 3;
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break;
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case 8:
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break;
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default:
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sprintf(msg, "Can't discover socket interleave");
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return -EINVAL;
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}
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*socket = sad_interleave[idx];
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edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
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idx, sad_way, *socket);
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} else {
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/* Ivy Bridge's SAD mode doesn't support XOR interleave mode */
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idx = (addr >> 6) & 7;
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switch (sad_way) {
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case 1:
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idx = 0;
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break;
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case 2:
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idx = idx & 1;
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break;
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case 4:
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idx = idx & 3;
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break;
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case 8:
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break;
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default:
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sprintf(msg, "Can't discover socket interleave");
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return -EINVAL;
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pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
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*socket = sad_pkg_socket(pkg);
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sad_ha = sad_pkg_ha(pkg);
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edac_dbg(0, "SAD interleave package: %d = CPU socket %d, HA %d\n",
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idx, *socket, sad_ha);
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}
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*socket = sad_interleave[idx];
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edac_dbg(0, "SAD interleave index: %d (wayness %d) = CPU socket %d\n",
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idx, sad_way, *socket);
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/*
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* Move to the proper node structure, in order to access the
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@ -923,9 +1060,16 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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* Step 2) Get memory channel
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*/
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prv = 0;
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if (pvt->info.type == SANDY_BRIDGE)
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pci_ha = pvt->pci_ha0;
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else {
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if (sad_ha)
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pci_ha = pvt->pci_ha1;
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else
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pci_ha = pvt->pci_ha0;
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}
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for (n_tads = 0; n_tads < MAX_TAD; n_tads++) {
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pci_read_config_dword(pvt->pci_ha0, tad_dram_rule[n_tads],
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®);
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pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®);
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limit = TAD_LIMIT(reg);
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if (limit <= prv) {
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sprintf(msg, "Can't discover the memory channel");
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@ -935,14 +1079,13 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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break;
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prv = limit;
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}
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if (n_tads == MAX_TAD) {
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sprintf(msg, "Can't discover the memory channel");
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return -EINVAL;
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}
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ch_way = TAD_CH(reg) + 1;
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sck_way = TAD_SOCK(reg) + 1;
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/*
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* FIXME: Is it right to always use channel 0 for offsets?
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*/
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pci_read_config_dword(pvt->pci_tad[0],
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tad_ch_nilv_offset[n_tads],
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&tad_offset);
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if (ch_way == 3)
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idx = addr >> 6;
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@ -972,6 +1115,10 @@ static int get_memory_error_data(struct mem_ctl_info *mci,
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}
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*channel_mask = 1 << base_ch;
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pci_read_config_dword(pvt->pci_tad[base_ch],
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tad_ch_nilv_offset[n_tads],
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&tad_offset);
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if (pvt->is_mirrored) {
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*channel_mask |= 1 << ((base_ch + 2) % 4);
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switch(ch_way) {
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@ -1347,6 +1494,131 @@ error:
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return -EINVAL;
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}
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static int ibridge_mci_bind_devs(struct mem_ctl_info *mci,
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struct sbridge_dev *sbridge_dev)
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{
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struct sbridge_pvt *pvt = mci->pvt_info;
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struct pci_dev *pdev, *tmp;
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int i, func, slot;
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bool mode_2ha = false;
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tmp = pci_get_device(PCI_VENDOR_ID_INTEL,
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PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA1, NULL);
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if (tmp) {
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mode_2ha = true;
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pci_dev_put(tmp);
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}
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for (i = 0; i < sbridge_dev->n_devs; i++) {
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pdev = sbridge_dev->pdev[i];
|
||||
if (!pdev)
|
||||
continue;
|
||||
slot = PCI_SLOT(pdev->devfn);
|
||||
func = PCI_FUNC(pdev->devfn);
|
||||
|
||||
switch (slot) {
|
||||
case 14:
|
||||
if (func == 0) {
|
||||
pvt->pci_ha0 = pdev;
|
||||
break;
|
||||
}
|
||||
goto error;
|
||||
case 15:
|
||||
switch (func) {
|
||||
case 0:
|
||||
pvt->pci_ta = pdev;
|
||||
break;
|
||||
case 1:
|
||||
pvt->pci_ras = pdev;
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
/* if we have 2 HAs active, channels 2 and 3
|
||||
* are in other device */
|
||||
if (mode_2ha)
|
||||
break;
|
||||
/* fall through */
|
||||
case 2:
|
||||
case 3:
|
||||
pvt->pci_tad[func - 2] = pdev;
|
||||
break;
|
||||
default:
|
||||
goto error;
|
||||
}
|
||||
break;
|
||||
case 17:
|
||||
if (func == 4) {
|
||||
pvt->pci_ddrio = pdev;
|
||||
break;
|
||||
} else if (func == 0) {
|
||||
if (!mode_2ha)
|
||||
pvt->pci_ddrio = pdev;
|
||||
break;
|
||||
}
|
||||
goto error;
|
||||
case 22:
|
||||
switch (func) {
|
||||
case 0:
|
||||
pvt->pci_sad0 = pdev;
|
||||
break;
|
||||
case 1:
|
||||
pvt->pci_br0 = pdev;
|
||||
break;
|
||||
case 2:
|
||||
pvt->pci_br1 = pdev;
|
||||
break;
|
||||
default:
|
||||
goto error;
|
||||
}
|
||||
break;
|
||||
case 28:
|
||||
if (func == 0) {
|
||||
pvt->pci_ha1 = pdev;
|
||||
break;
|
||||
}
|
||||
goto error;
|
||||
case 29:
|
||||
/* we shouldn't have this device if we have just one
|
||||
* HA present */
|
||||
WARN_ON(!mode_2ha);
|
||||
if (func == 2 || func == 3) {
|
||||
pvt->pci_tad[func] = pdev;
|
||||
break;
|
||||
}
|
||||
goto error;
|
||||
default:
|
||||
goto error;
|
||||
}
|
||||
|
||||
edac_dbg(0, "Associated PCI %02x.%02d.%d with dev = %p\n",
|
||||
sbridge_dev->bus,
|
||||
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
|
||||
pdev);
|
||||
}
|
||||
|
||||
/* Check if everything were registered */
|
||||
if (!pvt->pci_sad0 || !pvt->pci_ha0 || !pvt->pci_br0 ||
|
||||
!pvt->pci_br1 || !pvt->pci_tad || !pvt->pci_ras ||
|
||||
!pvt->pci_ta)
|
||||
goto enodev;
|
||||
|
||||
for (i = 0; i < NUM_CHANNELS; i++) {
|
||||
if (!pvt->pci_tad[i])
|
||||
goto enodev;
|
||||
}
|
||||
return 0;
|
||||
|
||||
enodev:
|
||||
sbridge_printk(KERN_ERR, "Some needed devices are missing\n");
|
||||
return -ENODEV;
|
||||
|
||||
error:
|
||||
sbridge_printk(KERN_ERR,
|
||||
"Device %d, function %d is out of the expected range\n",
|
||||
slot, func);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
Error check routines
|
||||
****************************************************************************/
|
||||
|
|
@ -1367,7 +1639,7 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
|
|||
bool ripv = GET_BITFIELD(m->mcgstatus, 0, 0);
|
||||
bool overflow = GET_BITFIELD(m->status, 62, 62);
|
||||
bool uncorrected_error = GET_BITFIELD(m->status, 61, 61);
|
||||
bool recoverable = GET_BITFIELD(m->status, 56, 56);
|
||||
bool recoverable;
|
||||
u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
|
||||
u32 mscod = GET_BITFIELD(m->status, 16, 31);
|
||||
u32 errcode = GET_BITFIELD(m->status, 0, 15);
|
||||
|
|
@ -1378,6 +1650,11 @@ static void sbridge_mce_output_error(struct mem_ctl_info *mci,
|
|||
int rc, dimm;
|
||||
char *area_type = NULL;
|
||||
|
||||
if (pvt->info.type == IVY_BRIDGE)
|
||||
recoverable = true;
|
||||
else
|
||||
recoverable = GET_BITFIELD(m->status, 56, 56);
|
||||
|
||||
if (uncorrected_error) {
|
||||
if (ripv) {
|
||||
type = "FATAL";
|
||||
|
|
@ -1636,11 +1913,12 @@ static void sbridge_unregister_mci(struct sbridge_dev *sbridge_dev)
|
|||
sbridge_dev->mci = NULL;
|
||||
}
|
||||
|
||||
static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
|
||||
static int sbridge_register_mci(struct sbridge_dev *sbridge_dev, enum type type)
|
||||
{
|
||||
struct mem_ctl_info *mci;
|
||||
struct edac_mc_layer layers[2];
|
||||
struct sbridge_pvt *pvt;
|
||||
struct pci_dev *pdev = sbridge_dev->pdev[0];
|
||||
int rc;
|
||||
|
||||
/* Check the number of active and not disabled channels */
|
||||
|
|
@ -1662,7 +1940,7 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
|
|||
return -ENOMEM;
|
||||
|
||||
edac_dbg(0, "MC: mci = %p, dev = %p\n",
|
||||
mci, &sbridge_dev->pdev[0]->dev);
|
||||
mci, &pdev->dev);
|
||||
|
||||
pvt = mci->pvt_info;
|
||||
memset(pvt, 0, sizeof(*pvt));
|
||||
|
|
@ -1676,31 +1954,52 @@ static int sbridge_register_mci(struct sbridge_dev *sbridge_dev)
|
|||
mci->edac_cap = EDAC_FLAG_NONE;
|
||||
mci->mod_name = "sbridge_edac.c";
|
||||
mci->mod_ver = SBRIDGE_REVISION;
|
||||
mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
|
||||
mci->dev_name = pci_name(sbridge_dev->pdev[0]);
|
||||
mci->dev_name = pci_name(pdev);
|
||||
mci->ctl_page_to_phys = NULL;
|
||||
pvt->info.get_tolm = sbridge_get_tolm;
|
||||
pvt->info.get_tohm = sbridge_get_tohm;
|
||||
pvt->info.dram_rule = sbridge_dram_rule;
|
||||
pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
|
||||
pvt->info.interleave_list = sbridge_interleave_list;
|
||||
pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
|
||||
pvt->info.interleave_pkg = sbridge_interleave_pkg;
|
||||
|
||||
/* Set the function pointer to an actual operation function */
|
||||
mci->edac_check = sbridge_check_error;
|
||||
|
||||
/* Store pci devices at mci for faster access */
|
||||
rc = sbridge_mci_bind_devs(mci, sbridge_dev);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
pvt->info.type = type;
|
||||
if (type == IVY_BRIDGE) {
|
||||
pvt->info.rankcfgr = IB_RANK_CFG_A;
|
||||
pvt->info.get_tolm = ibridge_get_tolm;
|
||||
pvt->info.get_tohm = ibridge_get_tohm;
|
||||
pvt->info.dram_rule = ibridge_dram_rule;
|
||||
pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
|
||||
pvt->info.interleave_list = ibridge_interleave_list;
|
||||
pvt->info.max_interleave = ARRAY_SIZE(ibridge_interleave_list);
|
||||
pvt->info.interleave_pkg = ibridge_interleave_pkg;
|
||||
mci->ctl_name = kasprintf(GFP_KERNEL, "Ivy Bridge Socket#%d", mci->mc_idx);
|
||||
|
||||
/* Store pci devices at mci for faster access */
|
||||
rc = ibridge_mci_bind_devs(mci, sbridge_dev);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
} else {
|
||||
pvt->info.rankcfgr = SB_RANK_CFG_A;
|
||||
pvt->info.get_tolm = sbridge_get_tolm;
|
||||
pvt->info.get_tohm = sbridge_get_tohm;
|
||||
pvt->info.dram_rule = sbridge_dram_rule;
|
||||
pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
|
||||
pvt->info.interleave_list = sbridge_interleave_list;
|
||||
pvt->info.max_interleave = ARRAY_SIZE(sbridge_interleave_list);
|
||||
pvt->info.interleave_pkg = sbridge_interleave_pkg;
|
||||
mci->ctl_name = kasprintf(GFP_KERNEL, "Sandy Bridge Socket#%d", mci->mc_idx);
|
||||
|
||||
/* Store pci devices at mci for faster access */
|
||||
rc = sbridge_mci_bind_devs(mci, sbridge_dev);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
}
|
||||
|
||||
|
||||
/* Get dimm basic config and the memory layout */
|
||||
get_dimm_config(mci);
|
||||
get_memory_layout(mci);
|
||||
|
||||
/* record ptr to the generic device */
|
||||
mci->pdev = &sbridge_dev->pdev[0]->dev;
|
||||
mci->pdev = &pdev->dev;
|
||||
|
||||
/* add this new MC control structure to EDAC's list of MCs */
|
||||
if (unlikely(edac_mc_add_mc(mci))) {
|
||||
|
|
@ -1731,6 +2030,7 @@ static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
int rc;
|
||||
u8 mc, num_mc = 0;
|
||||
struct sbridge_dev *sbridge_dev;
|
||||
enum type type;
|
||||
|
||||
/* get the pci devices we want to reserve for our use */
|
||||
mutex_lock(&sbridge_edac_lock);
|
||||
|
|
@ -1744,7 +2044,13 @@ static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
}
|
||||
probed++;
|
||||
|
||||
rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
|
||||
if (pdev->device == PCI_DEVICE_ID_INTEL_IBRIDGE_IMC_HA0_TA) {
|
||||
rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_ibridge_table);
|
||||
type = IVY_BRIDGE;
|
||||
} else {
|
||||
rc = sbridge_get_all_devices(&num_mc, pci_dev_descr_sbridge_table);
|
||||
type = SANDY_BRIDGE;
|
||||
}
|
||||
if (unlikely(rc < 0))
|
||||
goto fail0;
|
||||
mc = 0;
|
||||
|
|
@ -1753,7 +2059,7 @@ static int sbridge_probe(struct pci_dev *pdev, const struct pci_device_id *id)
|
|||
edac_dbg(0, "Registering MC#%d (%d of %d)\n",
|
||||
mc, mc + 1, num_mc);
|
||||
sbridge_dev->mc = mc++;
|
||||
rc = sbridge_register_mci(sbridge_dev);
|
||||
rc = sbridge_register_mci(sbridge_dev, type);
|
||||
if (unlikely(rc < 0))
|
||||
goto fail1;
|
||||
}
|
||||
|
|
@ -1868,5 +2174,5 @@ MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
|
|||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
|
||||
MODULE_AUTHOR("Red Hat Inc. (http://www.redhat.com)");
|
||||
MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge memory controllers - "
|
||||
MODULE_DESCRIPTION("MC Driver for Intel Sandy Bridge and Ivy Bridge memory controllers - "
|
||||
SBRIDGE_REVISION);
|
||||
|
|
|
|||
Loading…
Reference in New Issue