ARM: 7950/1: mm: Fix stage-2 device memory attributes
The stage-2 memory attributes are distinct from the Hyp memory attributes and the Stage-1 memory attributes. We were using the stage-1 memory attributes for stage-2 mappings causing device mappings to be mapped as normal memory. Add the S2 equivalent defines for memory attributes and fix the comments explaining the defines while at it. Add a prot_pte_s2 field to the mem_type struct and fill out the field for device mappings accordingly. Cc: <stable@vger.kernel.org> [3.9+] Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -120,13 +120,16 @@
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/*
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* 2nd stage PTE definitions for LPAE.
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*/
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#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
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#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
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#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
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#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
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#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
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#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x0) << 2) /* strongly ordered */
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#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* normal inner write-through */
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#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* normal inner write-back */
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#define L_PTE_S2_MT_DEV_SHARED (_AT(pteval_t, 0x1) << 2) /* device */
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#define L_PTE_S2_MT_MASK (_AT(pteval_t, 0xf) << 2)
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#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
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#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
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#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
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#define L_PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
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/*
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* Hyp-mode PL2 PTE definitions for LPAE.
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@ -38,6 +38,7 @@ static inline pmd_t *pmd_off_k(unsigned long virt)
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struct mem_type {
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pteval_t prot_pte;
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pteval_t prot_pte_s2;
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pmdval_t prot_l1;
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pmdval_t prot_sect;
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unsigned int domain;
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@ -232,12 +232,16 @@ __setup("noalign", noalign_setup);
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#endif /* ifdef CONFIG_CPU_CP15 / else */
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#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
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#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
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#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
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static struct mem_type mem_types[] = {
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[MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */
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.prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
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L_PTE_SHARED,
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.prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
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s2_policy(L_PTE_S2_MT_DEV_SHARED) |
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L_PTE_SHARED,
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.prot_l1 = PMD_TYPE_TABLE,
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.prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
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.domain = DOMAIN_IO,
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@ -508,7 +512,8 @@ static void __init build_mem_type_table(void)
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cp = &cache_policies[cachepolicy];
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vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
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s2_pgprot = cp->pte_s2;
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hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte;
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hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
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s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
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/*
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* ARMv6 and above have extended page tables.
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