drm/dp: Add definition for Display Control DPCD Registers capability size
This is used when reading Display Control capability Registers on the sink device. cc: dri-devel@lists.freedesktop.org Signed-off-by: Yetunde Adebisi <yetundex.adebisi@intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1459865452-9138-2-git-send-email-yetundex.adebisi@intel.com
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@ -621,6 +621,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SI
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#define DP_BRANCH_OUI_HEADER_SIZE 0xc
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#define DP_BRANCH_OUI_HEADER_SIZE 0xc
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#define DP_RECEIVER_CAP_SIZE 0xf
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#define DP_RECEIVER_CAP_SIZE 0xf
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#define EDP_PSR_RECEIVER_CAP_SIZE 2
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#define EDP_PSR_RECEIVER_CAP_SIZE 2
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#define EDP_DISPLAY_CTL_CAP_SIZE 3
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void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
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