Merge branch 'ide-dcr' of git://git.kernel.org/pub/scm/linux/kernel/git/bart/misc
This commit is contained in:
commit
4e5b932c82
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@ -39,16 +39,6 @@
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#define DRV_NAME "alim15x3"
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/*
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* Allow UDMA on M1543C-E chipset for WDC disks that ignore CRC checking
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* (this is DANGEROUS and could result in data corruption).
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*/
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static int wdc_udma;
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module_param(wdc_udma, bool, 0);
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MODULE_PARM_DESC(wdc_udma,
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"allow UDMA on M1543C-E chipset for WDC disks (DANGEROUS)");
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/*
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* ALi devices are not plug in. Otherwise these static values would
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* need to go. They ought to go away anyway
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@ -132,7 +122,7 @@ static u8 ali_udma_filter(ide_drive_t *drive)
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if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
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if (drive->media != ide_disk)
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return 0;
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if (wdc_udma == 0 && chip_is_1543c_e &&
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if (chip_is_1543c_e &&
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strstr((char *)&drive->id[ATA_ID_PROD], "WDC "))
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return 0;
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}
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@ -20,14 +20,6 @@
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#define DRV_NAME "cmd64x"
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#define CMD_DEBUG 0
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#if CMD_DEBUG
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#define cmdprintk(x...) printk(x)
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#else
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#define cmdprintk(x...)
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#endif
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/*
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* CMD64x specific registers definition.
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*/
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@ -76,9 +68,6 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_
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{15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
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static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
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cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
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cycle_time, active_time);
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cycle_count = quantize_timing( cycle_time, clock_time);
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active_count = quantize_timing(active_time, clock_time);
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recovery_count = cycle_count - active_count;
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@ -94,9 +83,6 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_
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if (active_count > 16) /* shouldn't actually happen... */
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active_count = 16;
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cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
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cycle_count, active_count, recovery_count);
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/*
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* Convert values to internal chipset representation
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*/
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@ -106,7 +92,6 @@ static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_
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/* Program the active/recovery counts into the DRWTIM register */
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drwtim = (active_count << 4) | recovery_count;
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(void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
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cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
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}
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/*
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@ -150,7 +135,6 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
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if (setup_count > 5) /* shouldn't actually happen... */
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setup_count = 5;
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cmdprintk("Final address setup count: %d\n", setup_count);
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/*
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* Program the address setup clocks into the ARTTIM registers.
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@ -162,7 +146,6 @@ static void cmd64x_tune_pio(ide_drive_t *drive, const u8 pio)
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arttim &= ~0xc0;
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arttim |= setup_values[setup_count];
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(void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
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cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
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}
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/*
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@ -50,11 +50,6 @@
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#define DRV_NAME "cy82c693"
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/*
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* The following are used to debug the driver.
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*/
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#define CY82C693_DEBUG_INFO 0
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/*
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* NOTE: the value for busmaster timeout is tricky and I got it by
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* trial and error! By using a to low value will cause DMA timeouts
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@ -176,11 +171,6 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
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outb(index, CY82_INDEX_PORT);
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outb(data, CY82_DATA_PORT);
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#if CY82C693_DEBUG_INFO
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printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
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drive->name, hwif->channel, drive->dn & 1, mode & 3, single);
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#endif /* CY82C693_DEBUG_INFO */
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/*
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* note: below we set the value for Bus Master IDE TimeOut Register
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* I'm not absolutly sure what this does, but it solved my problem
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@ -194,11 +184,6 @@ static void cy82c693_set_dma_mode(ide_drive_t *drive, const u8 mode)
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data = BUSMASTER_TIMEOUT;
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outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
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outb(data, CY82_DATA_PORT);
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#if CY82C693_DEBUG_INFO
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printk(KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
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drive->name, data);
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#endif /* CY82C693_DEBUG_INFO */
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}
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static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
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@ -239,8 +224,6 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
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pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
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pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
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pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
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addrCtrl &= 0xF;
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} else {
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/*
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* set slave drive
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@ -257,17 +240,7 @@ static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
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pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
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pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
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pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
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addrCtrl >>= 4;
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addrCtrl &= 0xF;
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}
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#if CY82C693_DEBUG_INFO
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printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
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"(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
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drive->name, hwif->channel, drive->dn & 1,
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addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
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#endif /* CY82C693_DEBUG_INFO */
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}
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static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
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@ -21,8 +21,6 @@
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#define DRV_NAME "pdc202xx_old"
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#define PDC202XX_DEBUG_DRIVE_INFO 0
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static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
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static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
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@ -34,11 +32,6 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
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u8 AP = 0, BP = 0, CP = 0;
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u8 TA = 0, TB = 0, TC = 0;
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#if PDC202XX_DEBUG_DRIVE_INFO
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u32 drive_conf = 0;
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pci_read_config_dword(dev, drive_pci, &drive_conf);
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#endif
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/*
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* TODO: do this once per channel
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*/
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@ -89,14 +82,6 @@ static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
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pci_write_config_byte(dev, drive_pci + 1, BP | TB);
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pci_write_config_byte(dev, drive_pci + 2, CP | TC);
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}
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#if PDC202XX_DEBUG_DRIVE_INFO
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printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
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drive->name, ide_xfer_verbose(speed),
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drive->dn, drive_conf);
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pci_read_config_dword(dev, drive_pci, &drive_conf);
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printk("0x%08x\n", drive_conf);
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#endif
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}
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static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
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@ -632,12 +632,3 @@ module_exit(sis5513_ide_exit);
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MODULE_AUTHOR("Lionel Bouton, L C Chang, Andre Hedrick, Vojtech Pavlik");
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MODULE_DESCRIPTION("PCI driver module for SIS IDE");
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MODULE_LICENSE("GPL");
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/*
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* TODO:
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* - CLEANUP
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* - More checks in the config registers (force values instead of
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* relying on the BIOS setting them correctly).
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* - Further optimisations ?
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* . for example ATA66+ regs 0x48 & 0x4A
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*/
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@ -24,13 +24,6 @@
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#define DRV_NAME "sl82c105"
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#undef DEBUG
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#ifdef DEBUG
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#define DBG(arg) printk arg
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#else
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#define DBG(fmt,...)
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#endif
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/*
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* SL82C105 PCI config register 0x40 bits.
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*/
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@ -104,9 +97,6 @@ static void sl82c105_set_dma_mode(ide_drive_t *drive, const u8 speed)
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unsigned long timings = (unsigned long)ide_get_drivedata(drive);
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u16 drv_ctrl;
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DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
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drive->name, ide_xfer_verbose(speed)));
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drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
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/*
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@ -196,8 +186,6 @@ static void sl82c105_dma_start(ide_drive_t *drive)
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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int reg = 0x44 + drive->dn * 4;
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DBG(("%s(drive:%s)\n", __func__, drive->name));
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pci_write_config_word(dev, reg,
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(unsigned long)ide_get_drivedata(drive) >> 16);
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@ -209,8 +197,6 @@ static void sl82c105_dma_clear(ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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DBG(("sl82c105_dma_clear(drive:%s)\n", drive->name));
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sl82c105_reset_host(dev);
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}
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@ -218,11 +204,7 @@ static int sl82c105_dma_end(ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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int reg = 0x44 + drive->dn * 4;
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int ret;
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DBG(("%s(drive:%s)\n", __func__, drive->name));
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ret = ide_dma_end(drive);
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int ret = ide_dma_end(drive);
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pci_write_config_word(dev, reg,
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(unsigned long)ide_get_drivedata(drive));
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@ -239,8 +221,6 @@ static void sl82c105_resetproc(ide_drive_t *drive)
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struct pci_dev *dev = to_pci_dev(drive->hwif->dev);
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u32 val;
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DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
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pci_read_config_dword(dev, 0x40, &val);
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val |= (CTRL_P1F16 | CTRL_P0F16);
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pci_write_config_dword(dev, 0x40, val);
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@ -291,8 +271,6 @@ static int init_chipset_sl82c105(struct pci_dev *dev)
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{
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u32 val;
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DBG(("init_chipset_sl82c105()\n"));
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pci_read_config_dword(dev, 0x40, &val);
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val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
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pci_write_config_dword(dev, 0x40, val);
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