ARM: dts: imx7d-pico-pi: Move SoM related part to imx7d-pico.dtsi
imx7d-pico-pi board contains: - One SoM board (imx7d pico) - One base board (pi). In order to make it easier for adding support for other board variants, move the commom SoM part to the imx7d-pico.dtsi file. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Fabio Estevam
Shawn Guo
parent
a26aec533e
commit
4edbe6aa46
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@ -5,6 +5,9 @@
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#include "imx7d-pico.dtsi"
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/ {
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model = "TechNexion PICO-IMX7D Board and PI baseboard";
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compatible = "technexion,imx7d-pico-pi", "fsl,imx7d";
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sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "imx7-sgtl5000";
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@ -16,43 +19,14 @@
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};
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dailink_master: simple-audio-card,codec {
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sound-dai = <&codec>;
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sound-dai = <&sgtl5000>;
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clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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status = "okay";
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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codec: sgtl5000@a {
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sgtl5000: codec@a {
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#sound-dai-cells = <0>;
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reg = <0x0a>;
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compatible = "fsl,sgtl5000";
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@ -61,83 +35,3 @@
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VDDIO-supply = <®_vref_1v8>;
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};
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};
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&sai1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1>;
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assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
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<&clks IMX7D_SAI1_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
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assigned-clock-rates = <0>, <24576000>;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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vbus-supply = <®_usb_otg2_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&iomuxc {
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
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MX7D_PAD_SD2_WP__ENET1_MDC 0x3
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
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MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_sai1: sai1grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
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MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
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MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
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MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
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>;
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};
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pinctrl_uart5: uart5grp {
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fsl,pins = <
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
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MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
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>;
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};
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pinctrl_usbotg1_pwr: usbotg_pwr {
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fsl,pins = <
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MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
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>;
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};
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};
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@ -7,9 +7,6 @@
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#include "imx7d.dtsi"
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/ {
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model = "Technexion Pico i.MX7D Board";
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compatible = "technexion,imx7d-pico", "fsl,imx7d";
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/* Will be filled by the bootloader */
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memory@80000000 {
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device_type = "memory";
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@ -79,6 +76,37 @@
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assigned-clock-rates = <0>, <32768>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
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<&clks IMX7D_ENET1_TIME_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
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assigned-clock-rates = <0>, <100000000>;
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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status = "okay";
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};
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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};
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&i2c4 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c4>;
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@ -174,6 +202,35 @@
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};
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};
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&sai1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1>;
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assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>,
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<&clks IMX7D_SAI1_ROOT_CLK>;
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assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
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assigned-clock-rates = <0>, <24576000>;
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status = "okay";
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};
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&uart5 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart5>;
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assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>;
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assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
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status = "okay";
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};
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&usbotg1 {
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vbus-supply = <®_usb_otg1_vbus>;
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status = "okay";
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};
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&usbotg2 {
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vbus-supply = <®_usb_otg2_vbus>;
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dr_mode = "host";
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status = "okay";
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};
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&usdhc2 { /* Wifi SDIO */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_wifi_clk>;
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@ -208,6 +265,32 @@
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};
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&iomuxc {
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX7D_PAD_UART1_TX_DATA__I2C1_SDA 0x4000007f
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MX7D_PAD_UART1_RX_DATA__I2C1_SCL 0x4000007f
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
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MX7D_PAD_SD2_WP__ENET1_MDC 0x3
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MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
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MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
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MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
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MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
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MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
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MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
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MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
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MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
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MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
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MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
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MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
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MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
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>;
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};
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pinctrl_i2c4: i2c4grp {
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fsl,pins = <
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MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f
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@ -221,6 +304,28 @@
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>;
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};
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pinctrl_sai1: sai1grp {
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fsl,pins = <
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MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
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MX7D_PAD_ENET1_CRS__SAI1_TX_SYNC 0x1f
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MX7D_PAD_ENET1_COL__SAI1_TX_DATA0 0x30
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MX7D_PAD_ENET1_TX_CLK__SAI1_RX_DATA0 0x1f
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>;
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};
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pinctrl_uart5: uart5grp {
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fsl,pins = <
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MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x79
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MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x79
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>;
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};
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pinctrl_usbotg1_pwr: usbotg_pwr {
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fsl,pins = <
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MX7D_PAD_UART3_TX_DATA__GPIO4_IO5 0x14
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX7D_PAD_SD2_CMD__SD2_CMD 0x59
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