CRIS: Better ARTPEC-3 support for gpio
Add PWM support, correct comment for ARTPEC-3. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
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Jesper Nilsson
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97a644461d
commit
4f248d1cea
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@ -21,31 +21,35 @@
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* /dev/leds minor 2, Access to leds depending on kernelconfig
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*
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* For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
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* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
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* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
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* /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
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* /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
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* /dev/gpioa minor 0, 32 bit GPIO, each bit can change direction
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* /dev/gpiob minor 1, 32 bit GPIO, each bit can change direction
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* /dev/gpioc minor 3, 16 bit GPIO, each bit can change direction
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* /dev/gpiod minor 4, 32 bit GPIO, input only
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* /dev/leds minor 2, Access to leds depending on kernelconfig
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* /dev/pwm0 minor 16, PWM channel 0 on PA30
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* /dev/pwm1 minor 17, PWM channel 1 on PA31
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* /dev/pwm2 minor 18, PWM channel 2 on PB26
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* /dev/ppwm minor 19, PPWM channel
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*
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*/
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#ifndef _ASM_ETRAXGPIO_H
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#define _ASM_ETRAXGPIO_H
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#define GPIO_MINOR_FIRST 0
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#define ETRAXGPIO_IOCTYPE 43
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/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
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#ifdef CONFIG_ETRAX_ARCH_V10
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#define ETRAXGPIO_IOCTYPE 43
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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#define GPIO_MINOR_G 3
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#define GPIO_MINOR_LAST 3
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#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
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#endif
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#ifdef CONFIG_ETRAXFS
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#define ETRAXGPIO_IOCTYPE 43
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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@ -58,10 +62,10 @@
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#else
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#define GPIO_MINOR_LAST 5
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#endif
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#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST
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#endif
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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#define ETRAXGPIO_IOCTYPE 43
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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@ -73,12 +77,17 @@
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#else
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#define GPIO_MINOR_LAST 4
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#endif
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#define GPIO_MINOR_PWM0 16
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#define GPIO_MINOR_PWM1 17
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#define GPIO_MINOR_PWM2 18
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#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2
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#define GPIO_MINOR_FIRST_PWM 16
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#define GPIO_MINOR_PWM0 (GPIO_MINOR_FIRST_PWM+0)
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#define GPIO_MINOR_PWM1 (GPIO_MINOR_FIRST_PWM+1)
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#define GPIO_MINOR_PWM2 (GPIO_MINOR_FIRST_PWM+2)
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#define GPIO_MINOR_PPWM (GPIO_MINOR_FIRST_PWM+3)
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#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PPWM
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#define GPIO_MINOR_LAST_REAL GPIO_MINOR_LAST_PWM
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#endif
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/* supported ioctl _IOC_NR's */
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#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */
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@ -125,12 +134,10 @@
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*/
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#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */
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#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */
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#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input,
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* *arg updated with current input pins.
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*/
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#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output,
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* *arg updated with current output pins.
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*/
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#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input, */
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/* *arg updated with current input pins. */
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#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output, */
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/* *arg updated with current output pins. */
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/* The following ioctl's are applicable to the PWM channels only */
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@ -140,7 +147,8 @@ enum io_pwm_mode {
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PWM_OFF = 0, /* disabled, deallocated */
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PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */
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PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */
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PWM_VARFREQ = 3 /* individually configurable high/low periods */
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PWM_VARFREQ = 3, /* individually configurable high/low periods */
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PWM_SOFT = 4 /* software generated */
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};
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struct io_pwm_set_mode {
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@ -176,4 +184,56 @@ struct io_pwm_set_duty {
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int duty; /* 0..255 */
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};
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/* Returns information about the latest PWM pulse.
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* lo: Length of the latest low period, in units of 10ns.
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* hi: Length of the latest high period, in units of 10ns.
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* cnt: Time since last detected edge, in units of 10ns.
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*
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* The input source to PWM is decied by IO_PWM_SET_INPUT_SRC.
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*
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* NOTE: All PWM devices is connected to the same input source.
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*/
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#define IO_PWM_GET_PERIOD 0x23
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struct io_pwm_get_period {
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unsigned int lo;
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unsigned int hi;
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unsigned int cnt;
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};
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/* Sets the input source for the PWM input. For the src value see the
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* register description for gio:rw_pwm_in_cfg.
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*
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* NOTE: All PWM devices is connected to the same input source.
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*/
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#define IO_PWM_SET_INPUT_SRC 0x24
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struct io_pwm_set_input_src {
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unsigned int src; /* 0..7 */
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};
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/* Sets the duty cycles in steps of 1/256, 0 = 0%, 255 = 100% duty cycle */
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#define IO_PPWM_SET_DUTY 0x25
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struct io_ppwm_set_duty {
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int duty; /* 0..255 */
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};
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/* Configuraton struct for the IO_PWMCLK_SET_CONFIG ioctl to configure
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* PWM capable gpio pins:
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*/
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#define IO_PWMCLK_SETGET_CONFIG 0x26
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struct gpio_pwmclk_conf {
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unsigned int gpiopin; /* The pin number based on the opened device */
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unsigned int baseclk; /* The base clock to use, or sw will select one close*/
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unsigned int low; /* The number of low periods of the baseclk */
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unsigned int high; /* The number of high periods of the baseclk */
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};
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/* Examples:
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* To get a symmetric 12 MHz clock without knowing anything about the hardware:
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* baseclk = 12000000, low = 0, high = 0
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* To just get info of current setting:
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* baseclk = 0, low = 0, high = 0, the values will be updated by driver.
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*/
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#endif
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