Merge remote-tracking branches 'spi/topic/orion', 'spi/topic/pxa2xx', 'spi/topic/qup', 'spi/topic/rockchip' and 'spi/topic/samsung' into spi-next
This commit is contained in:
commit
4f9f4548a5
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@ -469,7 +469,6 @@ config SPI_S3C24XX_FIQ
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config SPI_S3C64XX
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tristate "Samsung S3C64XX series type SPI"
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depends on (PLAT_SAMSUNG || ARCH_EXYNOS)
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select S3C64XX_PL080 if ARCH_S3C64XX
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help
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SPI driver for Samsung S3C64XX and newer SoCs.
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@ -28,7 +28,12 @@
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/* Runtime PM autosuspend timeout: PM is fairly light on this driver */
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#define SPI_AUTOSUSPEND_TIMEOUT 200
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#define ORION_NUM_CHIPSELECTS 1 /* only one slave is supported*/
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/* Some SoCs using this driver support up to 8 chip selects.
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* It is up to the implementer to only use the chip selects
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* that are available.
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*/
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#define ORION_NUM_CHIPSELECTS 8
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#define ORION_SPI_WAIT_RDY_MAX_LOOP 2000 /* in usec */
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#define ORION_SPI_IF_CTRL_REG 0x00
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@ -44,6 +49,10 @@
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#define ARMADA_SPI_CLK_PRESCALE_MASK 0xDF
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#define ORION_SPI_MODE_MASK (ORION_SPI_MODE_CPOL | \
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ORION_SPI_MODE_CPHA)
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#define ORION_SPI_CS_MASK 0x1C
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#define ORION_SPI_CS_SHIFT 2
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#define ORION_SPI_CS(cs) ((cs << ORION_SPI_CS_SHIFT) & \
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ORION_SPI_CS_MASK)
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enum orion_spi_type {
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ORION_SPI,
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@ -215,9 +224,18 @@ orion_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
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return 0;
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}
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static void orion_spi_set_cs(struct orion_spi *orion_spi, int enable)
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static void orion_spi_set_cs(struct spi_device *spi, bool enable)
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{
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if (enable)
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struct orion_spi *orion_spi;
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orion_spi = spi_master_get_devdata(spi->master);
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orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, ORION_SPI_CS_MASK);
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orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG,
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ORION_SPI_CS(spi->chip_select));
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/* Chip select logic is inverted from spi_set_cs */
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if (!enable)
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orion_spi_setbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
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else
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orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
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@ -332,64 +350,31 @@ out:
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return xfer->len - count;
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}
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static int orion_spi_transfer_one_message(struct spi_master *master,
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struct spi_message *m)
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static int orion_spi_transfer_one(struct spi_master *master,
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struct spi_device *spi,
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struct spi_transfer *t)
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{
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struct orion_spi *orion_spi = spi_master_get_devdata(master);
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struct spi_device *spi = m->spi;
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struct spi_transfer *t = NULL;
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int par_override = 0;
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int status = 0;
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int cs_active = 0;
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/* Load defaults */
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status = orion_spi_setup_transfer(spi, NULL);
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status = orion_spi_setup_transfer(spi, t);
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if (status < 0)
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goto msg_done;
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return status;
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list_for_each_entry(t, &m->transfers, transfer_list) {
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if (par_override || t->speed_hz || t->bits_per_word) {
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par_override = 1;
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status = orion_spi_setup_transfer(spi, t);
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if (status < 0)
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break;
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if (!t->speed_hz && !t->bits_per_word)
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par_override = 0;
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}
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if (t->len)
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orion_spi_write_read(spi, t);
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if (!cs_active) {
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orion_spi_set_cs(orion_spi, 1);
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cs_active = 1;
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}
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return status;
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}
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if (t->len)
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m->actual_length += orion_spi_write_read(spi, t);
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (t->cs_change) {
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orion_spi_set_cs(orion_spi, 0);
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cs_active = 0;
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}
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}
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msg_done:
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if (cs_active)
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orion_spi_set_cs(orion_spi, 0);
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m->status = status;
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spi_finalize_current_message(master);
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return 0;
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static int orion_spi_setup(struct spi_device *spi)
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{
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return orion_spi_setup_transfer(spi, NULL);
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}
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static int orion_spi_reset(struct orion_spi *orion_spi)
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{
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/* Verify that the CS is deasserted */
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orion_spi_set_cs(orion_spi, 0);
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orion_spi_clrbits(orion_spi, ORION_SPI_IF_CTRL_REG, 0x1);
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return 0;
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}
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@ -442,9 +427,10 @@ static int orion_spi_probe(struct platform_device *pdev)
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/* we support only mode 0, and no options */
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master->mode_bits = SPI_CPHA | SPI_CPOL;
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master->transfer_one_message = orion_spi_transfer_one_message;
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master->set_cs = orion_spi_set_cs;
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master->transfer_one = orion_spi_transfer_one;
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master->num_chipselect = ORION_NUM_CHIPSELECTS;
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master->setup = orion_spi_setup;
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master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
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master->auto_runtime_pm = true;
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@ -111,23 +111,24 @@ static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
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* by using ->dma_running.
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*/
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if (atomic_dec_and_test(&drv_data->dma_running)) {
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void __iomem *reg = drv_data->ioaddr;
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/*
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* If the other CPU is still handling the ROR interrupt we
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* might not know about the error yet. So we re-check the
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* ROR bit here before we clear the status register.
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*/
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if (!error) {
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u32 status = read_SSSR(reg) & drv_data->mask_sr;
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u32 status = pxa2xx_spi_read(drv_data, SSSR)
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& drv_data->mask_sr;
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error = status & SSSR_ROR;
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}
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/* Clear status & disable interrupts */
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write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
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pxa2xx_spi_write(drv_data, SSCR1,
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pxa2xx_spi_read(drv_data, SSCR1)
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& ~drv_data->dma_cr1);
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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if (!pxa25x_ssp_comp(drv_data))
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write_SSTO(0, reg);
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pxa2xx_spi_write(drv_data, SSTO, 0);
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if (!error) {
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pxa2xx_spi_unmap_dma_buffers(drv_data);
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@ -139,7 +140,9 @@ static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
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msg->state = pxa2xx_spi_next_transfer(drv_data);
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} else {
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/* In case we got an error we disable the SSP now */
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write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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pxa2xx_spi_write(drv_data, SSCR0,
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pxa2xx_spi_read(drv_data, SSCR0)
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& ~SSCR0_SSE);
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msg->state = ERROR_STATE;
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}
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@ -247,7 +250,7 @@ irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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{
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u32 status;
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status = read_SSSR(drv_data->ioaddr) & drv_data->mask_sr;
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status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
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if (status & SSSR_ROR) {
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dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
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@ -21,6 +21,7 @@
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#include <linux/spi/spi.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include <mach/dma.h>
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#include "spi-pxa2xx.h"
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#define DMA_INT_MASK (DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERR)
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@ -114,11 +115,11 @@ static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
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drv_data->dma_mapped = 0;
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}
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static int wait_ssp_rx_stall(void const __iomem *ioaddr)
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static int wait_ssp_rx_stall(struct driver_data *drv_data)
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{
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unsigned long limit = loops_per_jiffy << 1;
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while ((read_SSSR(ioaddr) & SSSR_BSY) && --limit)
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while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit)
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cpu_relax();
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return limit;
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@ -137,17 +138,18 @@ static int wait_dma_channel_stop(int channel)
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static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
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const char *msg)
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{
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void __iomem *reg = drv_data->ioaddr;
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/* Stop and reset */
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DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
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pxa2xx_spi_write(drv_data, SSCR1,
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pxa2xx_spi_read(drv_data, SSCR1)
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& ~drv_data->dma_cr1);
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if (!pxa25x_ssp_comp(drv_data))
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write_SSTO(0, reg);
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pxa2xx_spi_write(drv_data, SSTO, 0);
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pxa2xx_spi_flush(drv_data);
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write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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pxa2xx_spi_write(drv_data, SSCR0,
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pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
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pxa2xx_spi_unmap_dma_buffers(drv_data);
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@ -159,11 +161,12 @@ static void pxa2xx_spi_dma_error_stop(struct driver_data *drv_data,
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static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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struct spi_message *msg = drv_data->cur_msg;
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/* Clear and disable interrupts on SSP and DMA channels*/
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write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
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pxa2xx_spi_write(drv_data, SSCR1,
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pxa2xx_spi_read(drv_data, SSCR1)
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& ~drv_data->dma_cr1);
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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DCSR(drv_data->tx_channel) = RESET_DMA_CHANNEL;
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DCSR(drv_data->rx_channel) = RESET_DMA_CHANNEL;
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@ -224,7 +227,7 @@ void pxa2xx_spi_dma_handler(int channel, void *data)
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&& (drv_data->ssp_type == PXA25x_SSP)) {
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/* Wait for rx to stall */
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if (wait_ssp_rx_stall(drv_data->ioaddr) == 0)
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if (wait_ssp_rx_stall(drv_data) == 0)
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dev_err(&drv_data->pdev->dev,
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"dma_handler: ssp rx stall failed\n");
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@ -236,9 +239,8 @@ void pxa2xx_spi_dma_handler(int channel, void *data)
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irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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{
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u32 irq_status;
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void __iomem *reg = drv_data->ioaddr;
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irq_status = read_SSSR(reg) & drv_data->mask_sr;
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irq_status = pxa2xx_spi_read(drv_data, SSSR) & drv_data->mask_sr;
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if (irq_status & SSSR_ROR) {
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pxa2xx_spi_dma_error_stop(drv_data,
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"dma_transfer: fifo overrun");
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@ -248,7 +250,7 @@ irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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/* Check for false positive timeout */
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if ((irq_status & SSSR_TINT)
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&& (DCSR(drv_data->tx_channel) & DCSR_RUN)) {
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write_SSSR(SSSR_TINT, reg);
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pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
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return IRQ_HANDLED;
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}
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@ -257,7 +259,7 @@ irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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/* Clear and disable timeout interrupt, do the rest in
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* dma_transfer_complete */
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if (!pxa25x_ssp_comp(drv_data))
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write_SSTO(0, reg);
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pxa2xx_spi_write(drv_data, SSTO, 0);
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/* finish this transfer, start the next */
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pxa2xx_spi_dma_transfer_complete(drv_data);
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@ -41,8 +41,6 @@ MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:pxa2xx-spi");
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#define MAX_BUSES 3
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#define TIMOUT_DFLT 1000
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/*
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@ -158,7 +156,6 @@ pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
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|
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static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
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{
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void __iomem *reg = drv_data->ioaddr;
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u32 mask;
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switch (drv_data->ssp_type) {
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|
@ -170,7 +167,7 @@ static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
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break;
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}
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return (read_SSSR(reg) & mask) == mask;
|
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return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
|
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}
|
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|
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static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
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|
@ -249,9 +246,6 @@ static void lpss_ssp_setup(struct driver_data *drv_data)
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unsigned offset = 0x400;
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u32 value, orig;
|
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|
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if (!is_lpss_ssp(drv_data))
|
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return;
|
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|
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/*
|
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* Perform auto-detection of the LPSS SSP private registers. They
|
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* can be either at 1k or 2k offset from the base address.
|
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|
@ -300,9 +294,6 @@ static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
|
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{
|
||||
u32 value;
|
||||
|
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if (!is_lpss_ssp(drv_data))
|
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return;
|
||||
|
||||
value = __lpss_ssp_read_priv(drv_data, SPI_CS_CONTROL);
|
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if (enable)
|
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value &= ~SPI_CS_CONTROL_CS_HIGH;
|
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|
@ -316,7 +307,7 @@ static void cs_assert(struct driver_data *drv_data)
|
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struct chip_data *chip = drv_data->cur_chip;
|
||||
|
||||
if (drv_data->ssp_type == CE4100_SSP) {
|
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write_SSSR(drv_data->cur_chip->frm, drv_data->ioaddr);
|
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pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
|
||||
return;
|
||||
}
|
||||
|
||||
|
@ -330,7 +321,8 @@ static void cs_assert(struct driver_data *drv_data)
|
|||
return;
|
||||
}
|
||||
|
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lpss_ssp_cs_control(drv_data, true);
|
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if (is_lpss_ssp(drv_data))
|
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lpss_ssp_cs_control(drv_data, true);
|
||||
}
|
||||
|
||||
static void cs_deassert(struct driver_data *drv_data)
|
||||
|
@ -350,20 +342,18 @@ static void cs_deassert(struct driver_data *drv_data)
|
|||
return;
|
||||
}
|
||||
|
||||
lpss_ssp_cs_control(drv_data, false);
|
||||
if (is_lpss_ssp(drv_data))
|
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lpss_ssp_cs_control(drv_data, false);
|
||||
}
|
||||
|
||||
int pxa2xx_spi_flush(struct driver_data *drv_data)
|
||||
{
|
||||
unsigned long limit = loops_per_jiffy << 1;
|
||||
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
do {
|
||||
while (read_SSSR(reg) & SSSR_RNE) {
|
||||
read_SSDR(reg);
|
||||
}
|
||||
} while ((read_SSSR(reg) & SSSR_BSY) && --limit);
|
||||
while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
|
||||
pxa2xx_spi_read(drv_data, SSDR);
|
||||
} while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
|
||||
write_SSSR_CS(drv_data, SSSR_ROR);
|
||||
|
||||
return limit;
|
||||
|
@ -371,14 +361,13 @@ int pxa2xx_spi_flush(struct driver_data *drv_data)
|
|||
|
||||
static int null_writer(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
u8 n_bytes = drv_data->n_bytes;
|
||||
|
||||
if (pxa2xx_spi_txfifo_full(drv_data)
|
||||
|| (drv_data->tx == drv_data->tx_end))
|
||||
return 0;
|
||||
|
||||
write_SSDR(0, reg);
|
||||
pxa2xx_spi_write(drv_data, SSDR, 0);
|
||||
drv_data->tx += n_bytes;
|
||||
|
||||
return 1;
|
||||
|
@ -386,12 +375,11 @@ static int null_writer(struct driver_data *drv_data)
|
|||
|
||||
static int null_reader(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
u8 n_bytes = drv_data->n_bytes;
|
||||
|
||||
while ((read_SSSR(reg) & SSSR_RNE)
|
||||
&& (drv_data->rx < drv_data->rx_end)) {
|
||||
read_SSDR(reg);
|
||||
while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
|
||||
&& (drv_data->rx < drv_data->rx_end)) {
|
||||
pxa2xx_spi_read(drv_data, SSDR);
|
||||
drv_data->rx += n_bytes;
|
||||
}
|
||||
|
||||
|
@ -400,13 +388,11 @@ static int null_reader(struct driver_data *drv_data)
|
|||
|
||||
static int u8_writer(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
if (pxa2xx_spi_txfifo_full(drv_data)
|
||||
|| (drv_data->tx == drv_data->tx_end))
|
||||
return 0;
|
||||
|
||||
write_SSDR(*(u8 *)(drv_data->tx), reg);
|
||||
pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
|
||||
++drv_data->tx;
|
||||
|
||||
return 1;
|
||||
|
@ -414,11 +400,9 @@ static int u8_writer(struct driver_data *drv_data)
|
|||
|
||||
static int u8_reader(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
while ((read_SSSR(reg) & SSSR_RNE)
|
||||
&& (drv_data->rx < drv_data->rx_end)) {
|
||||
*(u8 *)(drv_data->rx) = read_SSDR(reg);
|
||||
while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
|
||||
&& (drv_data->rx < drv_data->rx_end)) {
|
||||
*(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
|
||||
++drv_data->rx;
|
||||
}
|
||||
|
||||
|
@ -427,13 +411,11 @@ static int u8_reader(struct driver_data *drv_data)
|
|||
|
||||
static int u16_writer(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
if (pxa2xx_spi_txfifo_full(drv_data)
|
||||
|| (drv_data->tx == drv_data->tx_end))
|
||||
return 0;
|
||||
|
||||
write_SSDR(*(u16 *)(drv_data->tx), reg);
|
||||
pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
|
||||
drv_data->tx += 2;
|
||||
|
||||
return 1;
|
||||
|
@ -441,11 +423,9 @@ static int u16_writer(struct driver_data *drv_data)
|
|||
|
||||
static int u16_reader(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
while ((read_SSSR(reg) & SSSR_RNE)
|
||||
&& (drv_data->rx < drv_data->rx_end)) {
|
||||
*(u16 *)(drv_data->rx) = read_SSDR(reg);
|
||||
while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
|
||||
&& (drv_data->rx < drv_data->rx_end)) {
|
||||
*(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
|
||||
drv_data->rx += 2;
|
||||
}
|
||||
|
||||
|
@ -454,13 +434,11 @@ static int u16_reader(struct driver_data *drv_data)
|
|||
|
||||
static int u32_writer(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
if (pxa2xx_spi_txfifo_full(drv_data)
|
||||
|| (drv_data->tx == drv_data->tx_end))
|
||||
return 0;
|
||||
|
||||
write_SSDR(*(u32 *)(drv_data->tx), reg);
|
||||
pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
|
||||
drv_data->tx += 4;
|
||||
|
||||
return 1;
|
||||
|
@ -468,11 +446,9 @@ static int u32_writer(struct driver_data *drv_data)
|
|||
|
||||
static int u32_reader(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
while ((read_SSSR(reg) & SSSR_RNE)
|
||||
&& (drv_data->rx < drv_data->rx_end)) {
|
||||
*(u32 *)(drv_data->rx) = read_SSDR(reg);
|
||||
while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
|
||||
&& (drv_data->rx < drv_data->rx_end)) {
|
||||
*(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
|
||||
drv_data->rx += 4;
|
||||
}
|
||||
|
||||
|
@ -548,27 +524,25 @@ static void giveback(struct driver_data *drv_data)
|
|||
|
||||
static void reset_sccr1(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
struct chip_data *chip = drv_data->cur_chip;
|
||||
u32 sccr1_reg;
|
||||
|
||||
sccr1_reg = read_SSCR1(reg) & ~drv_data->int_cr1;
|
||||
sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
|
||||
sccr1_reg &= ~SSCR1_RFT;
|
||||
sccr1_reg |= chip->threshold;
|
||||
write_SSCR1(sccr1_reg, reg);
|
||||
pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
|
||||
}
|
||||
|
||||
static void int_error_stop(struct driver_data *drv_data, const char* msg)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
/* Stop and reset SSP */
|
||||
write_SSSR_CS(drv_data, drv_data->clear_sr);
|
||||
reset_sccr1(drv_data);
|
||||
if (!pxa25x_ssp_comp(drv_data))
|
||||
write_SSTO(0, reg);
|
||||
pxa2xx_spi_write(drv_data, SSTO, 0);
|
||||
pxa2xx_spi_flush(drv_data);
|
||||
write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
|
||||
pxa2xx_spi_write(drv_data, SSCR0,
|
||||
pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
|
||||
|
||||
dev_err(&drv_data->pdev->dev, "%s\n", msg);
|
||||
|
||||
|
@ -578,13 +552,11 @@ static void int_error_stop(struct driver_data *drv_data, const char* msg)
|
|||
|
||||
static void int_transfer_complete(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
/* Stop SSP */
|
||||
write_SSSR_CS(drv_data, drv_data->clear_sr);
|
||||
reset_sccr1(drv_data);
|
||||
if (!pxa25x_ssp_comp(drv_data))
|
||||
write_SSTO(0, reg);
|
||||
pxa2xx_spi_write(drv_data, SSTO, 0);
|
||||
|
||||
/* Update total byte transferred return count actual bytes read */
|
||||
drv_data->cur_msg->actual_length += drv_data->len -
|
||||
|
@ -603,12 +575,10 @@ static void int_transfer_complete(struct driver_data *drv_data)
|
|||
|
||||
static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
|
||||
drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
|
||||
|
||||
u32 irq_mask = (read_SSCR1(reg) & SSCR1_TIE) ?
|
||||
drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
|
||||
|
||||
u32 irq_status = read_SSSR(reg) & irq_mask;
|
||||
u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
|
||||
|
||||
if (irq_status & SSSR_ROR) {
|
||||
int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
|
||||
|
@ -616,7 +586,7 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
|
|||
}
|
||||
|
||||
if (irq_status & SSSR_TINT) {
|
||||
write_SSSR(SSSR_TINT, reg);
|
||||
pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
|
||||
if (drv_data->read(drv_data)) {
|
||||
int_transfer_complete(drv_data);
|
||||
return IRQ_HANDLED;
|
||||
|
@ -640,7 +610,7 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
|
|||
u32 bytes_left;
|
||||
u32 sccr1_reg;
|
||||
|
||||
sccr1_reg = read_SSCR1(reg);
|
||||
sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
|
||||
sccr1_reg &= ~SSCR1_TIE;
|
||||
|
||||
/*
|
||||
|
@ -666,7 +636,7 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
|
|||
|
||||
pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
|
||||
}
|
||||
write_SSCR1(sccr1_reg, reg);
|
||||
pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
|
||||
}
|
||||
|
||||
/* We did something */
|
||||
|
@ -676,7 +646,6 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
|
|||
static irqreturn_t ssp_int(int irq, void *dev_id)
|
||||
{
|
||||
struct driver_data *drv_data = dev_id;
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
u32 sccr1_reg;
|
||||
u32 mask = drv_data->mask_sr;
|
||||
u32 status;
|
||||
|
@ -696,11 +665,11 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
|
|||
* are all set to one. That means that the device is already
|
||||
* powered off.
|
||||
*/
|
||||
status = read_SSSR(reg);
|
||||
status = pxa2xx_spi_read(drv_data, SSSR);
|
||||
if (status == ~0)
|
||||
return IRQ_NONE;
|
||||
|
||||
sccr1_reg = read_SSCR1(reg);
|
||||
sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
|
||||
|
||||
/* Ignore possible writes if we don't need to write */
|
||||
if (!(sccr1_reg & SSCR1_TIE))
|
||||
|
@ -711,10 +680,14 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
|
|||
|
||||
if (!drv_data->cur_msg) {
|
||||
|
||||
write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
|
||||
write_SSCR1(read_SSCR1(reg) & ~drv_data->int_cr1, reg);
|
||||
pxa2xx_spi_write(drv_data, SSCR0,
|
||||
pxa2xx_spi_read(drv_data, SSCR0)
|
||||
& ~SSCR0_SSE);
|
||||
pxa2xx_spi_write(drv_data, SSCR1,
|
||||
pxa2xx_spi_read(drv_data, SSCR1)
|
||||
& ~drv_data->int_cr1);
|
||||
if (!pxa25x_ssp_comp(drv_data))
|
||||
write_SSTO(0, reg);
|
||||
pxa2xx_spi_write(drv_data, SSTO, 0);
|
||||
write_SSSR_CS(drv_data, drv_data->clear_sr);
|
||||
|
||||
dev_err(&drv_data->pdev->dev,
|
||||
|
@ -783,7 +756,6 @@ static void pump_transfers(unsigned long data)
|
|||
struct spi_transfer *transfer = NULL;
|
||||
struct spi_transfer *previous = NULL;
|
||||
struct chip_data *chip = NULL;
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
u32 clk_div = 0;
|
||||
u8 bits = 0;
|
||||
u32 speed = 0;
|
||||
|
@ -927,7 +899,7 @@ static void pump_transfers(unsigned long data)
|
|||
|
||||
/* Clear status and start DMA engine */
|
||||
cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
|
||||
write_SSSR(drv_data->clear_sr, reg);
|
||||
pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
|
||||
|
||||
pxa2xx_spi_dma_start(drv_data);
|
||||
} else {
|
||||
|
@ -940,39 +912,43 @@ static void pump_transfers(unsigned long data)
|
|||
}
|
||||
|
||||
if (is_lpss_ssp(drv_data)) {
|
||||
if ((read_SSIRF(reg) & 0xff) != chip->lpss_rx_threshold)
|
||||
write_SSIRF(chip->lpss_rx_threshold, reg);
|
||||
if ((read_SSITF(reg) & 0xffff) != chip->lpss_tx_threshold)
|
||||
write_SSITF(chip->lpss_tx_threshold, reg);
|
||||
if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
|
||||
!= chip->lpss_rx_threshold)
|
||||
pxa2xx_spi_write(drv_data, SSIRF,
|
||||
chip->lpss_rx_threshold);
|
||||
if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
|
||||
!= chip->lpss_tx_threshold)
|
||||
pxa2xx_spi_write(drv_data, SSITF,
|
||||
chip->lpss_tx_threshold);
|
||||
}
|
||||
|
||||
if (is_quark_x1000_ssp(drv_data) &&
|
||||
(read_DDS_RATE(reg) != chip->dds_rate))
|
||||
write_DDS_RATE(chip->dds_rate, reg);
|
||||
(pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
|
||||
pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
|
||||
|
||||
/* see if we need to reload the config registers */
|
||||
if ((read_SSCR0(reg) != cr0) ||
|
||||
(read_SSCR1(reg) & change_mask) != (cr1 & change_mask)) {
|
||||
|
||||
if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
|
||||
|| (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
|
||||
!= (cr1 & change_mask)) {
|
||||
/* stop the SSP, and update the other bits */
|
||||
write_SSCR0(cr0 & ~SSCR0_SSE, reg);
|
||||
pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
|
||||
if (!pxa25x_ssp_comp(drv_data))
|
||||
write_SSTO(chip->timeout, reg);
|
||||
pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
|
||||
/* first set CR1 without interrupt and service enables */
|
||||
write_SSCR1(cr1 & change_mask, reg);
|
||||
pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
|
||||
/* restart the SSP */
|
||||
write_SSCR0(cr0, reg);
|
||||
pxa2xx_spi_write(drv_data, SSCR0, cr0);
|
||||
|
||||
} else {
|
||||
if (!pxa25x_ssp_comp(drv_data))
|
||||
write_SSTO(chip->timeout, reg);
|
||||
pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
|
||||
}
|
||||
|
||||
cs_assert(drv_data);
|
||||
|
||||
/* after chip select, release the data by enabling service
|
||||
* requests and interrupts, without changing any mode bits */
|
||||
write_SSCR1(cr1, reg);
|
||||
pxa2xx_spi_write(drv_data, SSCR1, cr1);
|
||||
}
|
||||
|
||||
static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
|
||||
|
@ -1001,8 +977,8 @@ static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
|
|||
struct driver_data *drv_data = spi_master_get_devdata(master);
|
||||
|
||||
/* Disable the SSP now */
|
||||
write_SSCR0(read_SSCR0(drv_data->ioaddr) & ~SSCR0_SSE,
|
||||
drv_data->ioaddr);
|
||||
pxa2xx_spi_write(drv_data, SSCR0,
|
||||
pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -1285,6 +1261,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
|
|||
struct driver_data *drv_data;
|
||||
struct ssp_device *ssp;
|
||||
int status;
|
||||
u32 tmp;
|
||||
|
||||
platform_info = dev_get_platdata(dev);
|
||||
if (!platform_info) {
|
||||
|
@ -1382,38 +1359,35 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
|
|||
drv_data->max_clk_rate = clk_get_rate(ssp->clk);
|
||||
|
||||
/* Load default SSP configuration */
|
||||
write_SSCR0(0, drv_data->ioaddr);
|
||||
pxa2xx_spi_write(drv_data, SSCR0, 0);
|
||||
switch (drv_data->ssp_type) {
|
||||
case QUARK_X1000_SSP:
|
||||
write_SSCR1(QUARK_X1000_SSCR1_RxTresh(
|
||||
RX_THRESH_QUARK_X1000_DFLT) |
|
||||
QUARK_X1000_SSCR1_TxTresh(
|
||||
TX_THRESH_QUARK_X1000_DFLT),
|
||||
drv_data->ioaddr);
|
||||
tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
|
||||
| QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
|
||||
pxa2xx_spi_write(drv_data, SSCR1, tmp);
|
||||
|
||||
/* using the Motorola SPI protocol and use 8 bit frame */
|
||||
write_SSCR0(QUARK_X1000_SSCR0_Motorola
|
||||
| QUARK_X1000_SSCR0_DataSize(8),
|
||||
drv_data->ioaddr);
|
||||
pxa2xx_spi_write(drv_data, SSCR0,
|
||||
QUARK_X1000_SSCR0_Motorola
|
||||
| QUARK_X1000_SSCR0_DataSize(8));
|
||||
break;
|
||||
default:
|
||||
write_SSCR1(SSCR1_RxTresh(RX_THRESH_DFLT) |
|
||||
SSCR1_TxTresh(TX_THRESH_DFLT),
|
||||
drv_data->ioaddr);
|
||||
write_SSCR0(SSCR0_SCR(2)
|
||||
| SSCR0_Motorola
|
||||
| SSCR0_DataSize(8),
|
||||
drv_data->ioaddr);
|
||||
tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
|
||||
SSCR1_TxTresh(TX_THRESH_DFLT);
|
||||
pxa2xx_spi_write(drv_data, SSCR1, tmp);
|
||||
tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
|
||||
pxa2xx_spi_write(drv_data, SSCR0, tmp);
|
||||
break;
|
||||
}
|
||||
|
||||
if (!pxa25x_ssp_comp(drv_data))
|
||||
write_SSTO(0, drv_data->ioaddr);
|
||||
pxa2xx_spi_write(drv_data, SSTO, 0);
|
||||
|
||||
if (!is_quark_x1000_ssp(drv_data))
|
||||
write_SSPSP(0, drv_data->ioaddr);
|
||||
pxa2xx_spi_write(drv_data, SSPSP, 0);
|
||||
|
||||
lpss_ssp_setup(drv_data);
|
||||
if (is_lpss_ssp(drv_data))
|
||||
lpss_ssp_setup(drv_data);
|
||||
|
||||
tasklet_init(&drv_data->pump_transfers, pump_transfers,
|
||||
(unsigned long)drv_data);
|
||||
|
@ -1456,7 +1430,7 @@ static int pxa2xx_spi_remove(struct platform_device *pdev)
|
|||
pm_runtime_get_sync(&pdev->dev);
|
||||
|
||||
/* Disable the SSP at the peripheral and SOC level */
|
||||
write_SSCR0(0, drv_data->ioaddr);
|
||||
pxa2xx_spi_write(drv_data, SSCR0, 0);
|
||||
clk_disable_unprepare(ssp->clk);
|
||||
|
||||
/* Release DMA */
|
||||
|
@ -1493,7 +1467,7 @@ static int pxa2xx_spi_suspend(struct device *dev)
|
|||
status = spi_master_suspend(drv_data->master);
|
||||
if (status != 0)
|
||||
return status;
|
||||
write_SSCR0(0, drv_data->ioaddr);
|
||||
pxa2xx_spi_write(drv_data, SSCR0, 0);
|
||||
|
||||
if (!pm_runtime_suspended(dev))
|
||||
clk_disable_unprepare(ssp->clk);
|
||||
|
@ -1514,7 +1488,8 @@ static int pxa2xx_spi_resume(struct device *dev)
|
|||
clk_prepare_enable(ssp->clk);
|
||||
|
||||
/* Restore LPSS private register bits */
|
||||
lpss_ssp_setup(drv_data);
|
||||
if (is_lpss_ssp(drv_data))
|
||||
lpss_ssp_setup(drv_data);
|
||||
|
||||
/* Start the queue running */
|
||||
status = spi_master_resume(drv_data->master);
|
||||
|
|
|
@ -115,23 +115,17 @@ struct chip_data {
|
|||
void (*cs_control)(u32 command);
|
||||
};
|
||||
|
||||
#define DEFINE_SSP_REG(reg, off) \
|
||||
static inline u32 read_##reg(void const __iomem *p) \
|
||||
{ return __raw_readl(p + (off)); } \
|
||||
\
|
||||
static inline void write_##reg(u32 v, void __iomem *p) \
|
||||
{ __raw_writel(v, p + (off)); }
|
||||
static inline u32 pxa2xx_spi_read(const struct driver_data *drv_data,
|
||||
unsigned reg)
|
||||
{
|
||||
return __raw_readl(drv_data->ioaddr + reg);
|
||||
}
|
||||
|
||||
DEFINE_SSP_REG(SSCR0, 0x00)
|
||||
DEFINE_SSP_REG(SSCR1, 0x04)
|
||||
DEFINE_SSP_REG(SSSR, 0x08)
|
||||
DEFINE_SSP_REG(SSITR, 0x0c)
|
||||
DEFINE_SSP_REG(SSDR, 0x10)
|
||||
DEFINE_SSP_REG(DDS_RATE, 0x28) /* DDS Clock Rate */
|
||||
DEFINE_SSP_REG(SSTO, 0x28)
|
||||
DEFINE_SSP_REG(SSPSP, 0x2c)
|
||||
DEFINE_SSP_REG(SSITF, SSITF)
|
||||
DEFINE_SSP_REG(SSIRF, SSIRF)
|
||||
static inline void pxa2xx_spi_write(const struct driver_data *drv_data,
|
||||
unsigned reg, u32 val)
|
||||
{
|
||||
__raw_writel(val, drv_data->ioaddr + reg);
|
||||
}
|
||||
|
||||
#define START_STATE ((void *)0)
|
||||
#define RUNNING_STATE ((void *)1)
|
||||
|
@ -155,13 +149,11 @@ static inline int pxa25x_ssp_comp(struct driver_data *drv_data)
|
|||
|
||||
static inline void write_SSSR_CS(struct driver_data *drv_data, u32 val)
|
||||
{
|
||||
void __iomem *reg = drv_data->ioaddr;
|
||||
|
||||
if (drv_data->ssp_type == CE4100_SSP ||
|
||||
drv_data->ssp_type == QUARK_X1000_SSP)
|
||||
val |= read_SSSR(reg) & SSSR_ALT_FRM_MASK;
|
||||
val |= pxa2xx_spi_read(drv_data, SSSR) & SSSR_ALT_FRM_MASK;
|
||||
|
||||
write_SSSR(val, reg);
|
||||
pxa2xx_spi_write(drv_data, SSSR, val);
|
||||
}
|
||||
|
||||
extern int pxa2xx_spi_flush(struct driver_data *drv_data);
|
||||
|
|
|
@ -337,7 +337,7 @@ static irqreturn_t spi_qup_qup_irq(int irq, void *dev_id)
|
|||
static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
|
||||
{
|
||||
struct spi_qup *controller = spi_master_get_devdata(spi->master);
|
||||
u32 config, iomode, mode;
|
||||
u32 config, iomode, mode, control;
|
||||
int ret, n_words, w_size;
|
||||
|
||||
if (spi->mode & SPI_LOOP && xfer->len > controller->in_fifo_sz) {
|
||||
|
@ -392,6 +392,15 @@ static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
|
|||
|
||||
writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
|
||||
|
||||
control = readl_relaxed(controller->base + SPI_IO_CONTROL);
|
||||
|
||||
if (spi->mode & SPI_CPOL)
|
||||
control |= SPI_IO_C_CLK_IDLE_HIGH;
|
||||
else
|
||||
control &= ~SPI_IO_C_CLK_IDLE_HIGH;
|
||||
|
||||
writel_relaxed(control, controller->base + SPI_IO_CONTROL);
|
||||
|
||||
config = readl_relaxed(controller->base + SPI_CONFIG);
|
||||
|
||||
if (spi->mode & SPI_LOOP)
|
||||
|
|
|
@ -437,6 +437,7 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
|
|||
rs->state &= ~TXBUSY;
|
||||
spin_unlock_irqrestore(&rs->lock, flags);
|
||||
|
||||
rxdesc = NULL;
|
||||
if (rs->rx) {
|
||||
rxconf.direction = rs->dma_rx.direction;
|
||||
rxconf.src_addr = rs->dma_rx.addr;
|
||||
|
@ -453,6 +454,7 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
|
|||
rxdesc->callback_param = rs;
|
||||
}
|
||||
|
||||
txdesc = NULL;
|
||||
if (rs->tx) {
|
||||
txconf.direction = rs->dma_tx.direction;
|
||||
txconf.dst_addr = rs->dma_tx.addr;
|
||||
|
@ -470,7 +472,7 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
|
|||
}
|
||||
|
||||
/* rx must be started before tx due to spi instinct */
|
||||
if (rs->rx) {
|
||||
if (rxdesc) {
|
||||
spin_lock_irqsave(&rs->lock, flags);
|
||||
rs->state |= RXBUSY;
|
||||
spin_unlock_irqrestore(&rs->lock, flags);
|
||||
|
@ -478,7 +480,7 @@ static void rockchip_spi_prepare_dma(struct rockchip_spi *rs)
|
|||
dma_async_issue_pending(rs->dma_rx.ch);
|
||||
}
|
||||
|
||||
if (rs->tx) {
|
||||
if (txdesc) {
|
||||
spin_lock_irqsave(&rs->lock, flags);
|
||||
rs->state |= TXBUSY;
|
||||
spin_unlock_irqrestore(&rs->lock, flags);
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
#define SSDR (0x10) /* SSP Data Write/Data Read Register */
|
||||
|
||||
#define SSTO (0x28) /* SSP Time Out Register */
|
||||
#define DDS_RATE (0x28) /* SSP DDS Clock Rate Register (Intel Quark) */
|
||||
#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
|
||||
#define SSTSA (0x30) /* SSP Tx Timeslot Active */
|
||||
#define SSRSA (0x34) /* SSP Rx Timeslot Active */
|
||||
|
|
|
@ -53,7 +53,6 @@ struct pxa2xx_spi_chip {
|
|||
#if defined(CONFIG_ARCH_PXA) || defined(CONFIG_ARCH_MMP)
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
|
||||
|
||||
|
|
Loading…
Reference in New Issue