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KVM: MIPS/Emulate: Adapt T&E CACHE emulation for Octeon 

Cache management is implemented separately for Cavium Octeon CPUs, so
r4k_blast_[id]cache aren't available. Instead for Octeon perform a local
icache flush using local_flush_icache_range(), and for other platforms
which don't use c-r4k.c use __flush_cache_all() / flush_icache_all().

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Radim Krčmář" <rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Daney <david.daney@cavium.com>
Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
This commit is contained in:
James Hogan 2017-03-14 10:25:45 +00:00
parent 7d8a528d19
commit 4fa9de5a64
2 changed files with 28 additions and 3 deletions
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30
arch/mips/kvm/emulate.c
View File

@ -1833,11 +1833,35 @@ enum emulation_result kvm_mips_emulate_cache(union mips_instruction inst,
vcpu->arch.pc, vcpu->arch.gprs[31], cache, op, base,
arch->gprs[base], offset);
if (cache == Cache_D)
if (cache == Cache_D) {
#ifdef CONFIG_CPU_R4K_CACHE_TLB
r4k_blast_dcache();
else if (cache == Cache_I)
#else
switch (boot_cpu_type()) {
case CPU_CAVIUM_OCTEON3:
/* locally flush icache */
local_flush_icache_range(0, 0);
break;
default:
__flush_cache_all();
break;
}
#endif
} else if (cache == Cache_I) {
#ifdef CONFIG_CPU_R4K_CACHE_TLB
r4k_blast_icache();
else {
#else
switch (boot_cpu_type()) {
case CPU_CAVIUM_OCTEON3:
/* locally flush icache */
local_flush_icache_range(0, 0);
break;
default:
flush_icache_all();
break;
}
#endif
} else {
kvm_err("%s: unsupported CACHE INDEX operation\n",
__func__);
return EMULATE_FAIL;

1
arch/mips/mm/cache.c
View File

@ -24,6 +24,7 @@
/* Cache operations. */
void (*flush_cache_all)(void);
void (*__flush_cache_all)(void);
EXPORT_SYMBOL_GPL(__flush_cache_all);
void (*flush_cache_mm)(struct mm_struct *mm);
void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
unsigned long end);