[ARM] S3C64XX: Add S3C6400 SDHCI setup support
Add support for S3C6400 SDHCI channels 0 and 1, making the GPIO code common to both S3C6400 and S3C6410. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
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e074f98032
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4faf686763
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@ -14,11 +14,18 @@ config CPU_S3C6400
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help
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Enable S3C6400 CPU support
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config S3C6400_SETUP_SDHCI
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bool
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help
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Internal configuration for default SDHCI
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setup for S3C6400.
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# S36400 Macchine support
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config MACH_SMDK6400
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bool "SMDK6400"
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select CPU_S3C6400
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select S3C_DEV_HSMMC
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select S3C6400_SETUP_SDHCI
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help
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Machine support for the Samsung SMDK6400
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@ -14,6 +14,10 @@ obj- :=
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obj-$(CONFIG_CPU_S3C6400) += s3c6400.o
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# setup support
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obj-$(CONFIG_S3C6400_SETUP_SDHCI) += setup-sdhci.o
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# Machine support
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obj-$(CONFIG_MACH_SMDK6400) += mach-smdk6400.o
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@ -40,7 +40,12 @@
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void __init s3c6400_map_io(void)
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{
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/* the i2c device is directly compatible with s3c2440 */
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/* setup SDHCI */
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s3c6400_default_sdhci0();
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s3c6400_default_sdhci1();
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/* the i2c devices are directly compatible with s3c2440 */
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s3c_i2c0_setname("s3c2440-i2c");
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}
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@ -0,0 +1,63 @@
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/* linux/arch/arm/mach-s3c6410/setup-sdhci.c
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*
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* Copyright 2008 Simtec Electronics
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C6410 - Helper functions for settign up SDHCI device(s) (HSMMC)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include <plat/regs-sdhci.h>
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#include <plat/sdhci.h>
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/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
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char *s3c6400_hsmmc_clksrcs[4] = {
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[0] = "hsmmc",
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[1] = "hsmmc",
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[2] = "mmc_bus",
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/* [3] = "48m", - note not succesfully used yet */
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};
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void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
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void __iomem *r,
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struct mmc_ios *ios,
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struct mmc_card *card)
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{
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u32 ctrl2, ctrl3;
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ctrl2 = readl(r + S3C_SDHCI_CONTROL2);
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ctrl2 &= S3C_SDHCI_CTRL2_SELBASECLK_MASK;
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ctrl2 |= (S3C64XX_SDHCI_CTRL2_ENSTAASYNCCLR |
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S3C64XX_SDHCI_CTRL2_ENCMDCNFMSK |
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S3C_SDHCI_CTRL2_ENFBCLKRX |
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S3C_SDHCI_CTRL2_DFCNT_NONE |
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S3C_SDHCI_CTRL2_ENCLKOUTHOLD);
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if (ios->clock < 25 * 1000000)
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ctrl3 = (S3C_SDHCI_CTRL3_FCSEL3 |
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S3C_SDHCI_CTRL3_FCSEL2 |
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S3C_SDHCI_CTRL3_FCSEL1 |
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S3C_SDHCI_CTRL3_FCSEL0);
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else
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ctrl3 = (S3C_SDHCI_CTRL3_FCSEL1 | S3C_SDHCI_CTRL3_FCSEL0);
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printk(KERN_INFO "%s: CTRL 2=%08x, 3=%08x\n", __func__, ctrl2, ctrl3);
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writel(ctrl2, r + S3C_SDHCI_CONTROL2);
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writel(ctrl3, r + S3C_SDHCI_CONTROL3);
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}
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@ -16,6 +16,7 @@ config CPU_S3C6410
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config S3C6410_SETUP_SDHCI
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bool
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select S3C64XX_SETUP_SDHCI_GPIO
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help
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Internal helper functions for S3C6410 based SDHCI systems
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@ -21,8 +21,6 @@
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#include <linux/mmc/card.h>
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#include <linux/mmc/host.h>
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#include <mach/gpio.h>
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#include <plat/gpio-cfg.h>
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#include <plat/regs-sdhci.h>
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#include <plat/sdhci.h>
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@ -35,22 +33,6 @@ char *s3c6410_hsmmc_clksrcs[4] = {
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/* [3] = "48m", - note not succesfully used yet */
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};
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void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
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{
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unsigned int gpio;
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unsigned int end;
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end = S3C64XX_GPG(2 + width);
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/* Set all the necessary GPG pins to special-function 0 */
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for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
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s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
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s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
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}
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s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
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}
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void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
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void __iomem *r,
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@ -84,19 +66,3 @@ void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
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writel(ctrl3, r + S3C_SDHCI_CONTROL3);
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}
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void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
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{
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unsigned int gpio;
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unsigned int end;
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end = S3C64XX_GPH(2 + width);
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/* Set all the necessary GPG pins to special-function 0 */
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for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
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s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
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s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
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}
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s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
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}
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@ -67,12 +67,52 @@ extern struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata;
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/* Helper function availablity */
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extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
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extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
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/* S3C6400 SDHCI setup */
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#ifdef CONFIG_S3C6400_SETUP_SDHCI
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extern char *s3c6400_hsmmc_clksrcs[4];
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#ifdef CONFIG_S3C_DEV_HSMMC
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extern void s3c6400_setup_sdhci_cfg_card(struct platform_device *dev,
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void __iomem *r,
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struct mmc_ios *ios,
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struct mmc_card *card);
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static inline void s3c6400_default_sdhci0(void)
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{
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s3c_hsmmc0_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
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s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
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s3c_hsmmc0_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
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}
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#else
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static inline void s3c6400_default_sdhci0(void) { }
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#endif /* CONFIG_S3C_DEV_HSMMC */
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#ifdef CONFIG_S3C_DEV_HSMMC1
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static inline void s3c6400_default_sdhci1(void)
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{
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s3c_hsmmc1_def_platdata.clocks = s3c6400_hsmmc_clksrcs;
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s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
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s3c_hsmmc1_def_platdata.cfg_card = s3c6400_setup_sdhci_cfg_card;
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}
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#else
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static inline void s3c6400_default_sdhci1(void) { }
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#endif /* CONFIG_S3C_DEV_HSMMC1 */
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#else
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static inline void s3c6400_default_sdhci0(void) { }
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static inline void s3c6400_default_sdhci1(void) { }
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#endif /* CONFIG_S3C6400_SETUP_SDHCI */
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/* S3C6410 SDHCI setup */
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#ifdef CONFIG_S3C6410_SETUP_SDHCI
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extern char *s3c6410_hsmmc_clksrcs[4];
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extern void s3c6410_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
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extern void s3c6410_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
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extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
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void __iomem *r,
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struct mmc_ios *ios,
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@ -82,7 +122,7 @@ extern void s3c6410_setup_sdhci0_cfg_card(struct platform_device *dev,
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static inline void s3c6410_default_sdhci0(void)
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{
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s3c_hsmmc0_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
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s3c_hsmmc0_def_platdata.cfg_gpio = s3c6410_setup_sdhci0_cfg_gpio;
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s3c_hsmmc0_def_platdata.cfg_gpio = s3c64xx_setup_sdhci0_cfg_gpio;
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s3c_hsmmc0_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
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}
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#else
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@ -93,7 +133,7 @@ static inline void s3c6410_default_sdhci0(void) { }
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static inline void s3c6410_default_sdhci1(void)
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{
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s3c_hsmmc1_def_platdata.clocks = s3c6410_hsmmc_clksrcs;
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s3c_hsmmc1_def_platdata.cfg_gpio = s3c6410_setup_sdhci1_cfg_gpio;
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s3c_hsmmc1_def_platdata.cfg_gpio = s3c64xx_setup_sdhci1_cfg_gpio;
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s3c_hsmmc1_def_platdata.cfg_card = s3c6410_setup_sdhci0_cfg_card;
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}
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#else
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@ -60,4 +60,9 @@ config S3C64XX_SETUP_FB_24BPP
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help
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Common setup code for S3C64XX with an 24bpp RGB display helper.
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config S3C64XX_SETUP_SDHCI_GPIO
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bool
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help
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Common setup code for S3C64XX SDHCI GPIO configurations
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endif
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@ -35,3 +35,4 @@ obj-$(CONFIG_PM) += irq-pm.o
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obj-$(CONFIG_S3C64XX_SETUP_I2C0) += setup-i2c0.o
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obj-$(CONFIG_S3C64XX_SETUP_I2C1) += setup-i2c1.o
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obj-$(CONFIG_S3C64XX_SETUP_FB_24BPP) += setup-fb-24bpp.o
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obj-$(CONFIG_S3C64XX_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
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@ -0,0 +1,55 @@
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/* linux/arch/arm/plat-s3c64xx/setup-sdhci-gpio.c
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*
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* S3C64XX - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/gpio.h>
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#include <plat/gpio-cfg.h>
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void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
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{
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unsigned int gpio;
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unsigned int end;
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end = S3C64XX_GPG(2 + width);
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/* Set all the necessary GPG pins to special-function 0 */
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for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
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s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
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s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
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}
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s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(2));
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}
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void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
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{
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unsigned int gpio;
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unsigned int end;
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end = S3C64XX_GPH(2 + width);
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/* Set all the necessary GPG pins to special-function 0 */
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for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
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s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
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s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
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}
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s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_UP);
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s3c_gpio_cfgpin(S3C64XX_GPG(6), S3C_GPIO_SFN(3));
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}
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