MIPS: Add and use watch register field definitions
The files watch.c and ptrace.c contain various magic masks for WatchLo/WatchHi register fields. Add some definitions to mipsregs.h for these registers and make use of them in both watch.c and ptrace.c, hopefully making them more readable. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12729/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -648,6 +648,24 @@
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/* FTLB probability bits for R6 */
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/* FTLB probability bits for R6 */
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#define MIPS_CONF7_FTLBP_SHIFT (18)
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#define MIPS_CONF7_FTLBP_SHIFT (18)
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/* WatchLo* register definitions */
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#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
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/* WatchHi* register definitions */
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#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
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#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
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#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
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#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
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#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
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#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
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#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
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#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
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#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
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#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
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#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
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#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
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#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
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/* MAAR bit definitions */
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/* MAAR bit definitions */
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#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
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#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
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#define MIPS_MAAR_ADDR_SHIFT 12
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#define MIPS_MAAR_ADDR_SHIFT 12
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@ -210,7 +210,8 @@ int ptrace_get_watch_regs(struct task_struct *child,
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for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
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for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
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__put_user(child->thread.watch.mips3264.watchlo[i],
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__put_user(child->thread.watch.mips3264.watchlo[i],
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&addr->WATCH_STYLE.watchlo[i]);
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&addr->WATCH_STYLE.watchlo[i]);
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__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
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__put_user(child->thread.watch.mips3264.watchhi[i] &
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(MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW),
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&addr->WATCH_STYLE.watchhi[i]);
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&addr->WATCH_STYLE.watchhi[i]);
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__put_user(boot_cpu_data.watch_reg_masks[i],
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__put_user(boot_cpu_data.watch_reg_masks[i],
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&addr->WATCH_STYLE.watch_masks[i]);
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&addr->WATCH_STYLE.watch_masks[i]);
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@ -252,12 +253,12 @@ int ptrace_set_watch_regs(struct task_struct *child,
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}
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}
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#endif
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#endif
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__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
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__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
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if (ht[i] & ~0xff8)
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if (ht[i] & ~MIPS_WATCHHI_MASK)
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return -EINVAL;
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return -EINVAL;
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}
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}
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/* Install them. */
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/* Install them. */
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for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
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for (i = 0; i < boot_cpu_data.watch_reg_use_cnt; i++) {
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if (lt[i] & 7)
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if (lt[i] & MIPS_WATCHLO_IRW)
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watch_active = 1;
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watch_active = 1;
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child->thread.watch.mips3264.watchlo[i] = lt[i];
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child->thread.watch.mips3264.watchlo[i] = lt[i];
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/* Set the G bit. */
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/* Set the G bit. */
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@ -25,16 +25,20 @@ void mips_install_watch_registers(struct task_struct *t)
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write_c0_watchlo3(watches->watchlo[3]);
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write_c0_watchlo3(watches->watchlo[3]);
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/* Write 1 to the I, R, and W bits to clear them, and
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/* Write 1 to the I, R, and W bits to clear them, and
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1 to G so all ASIDs are trapped. */
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1 to G so all ASIDs are trapped. */
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write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
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write_c0_watchhi3(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
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watches->watchhi[3]);
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case 3:
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case 3:
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write_c0_watchlo2(watches->watchlo[2]);
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write_c0_watchlo2(watches->watchlo[2]);
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write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
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write_c0_watchhi2(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
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watches->watchhi[2]);
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case 2:
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case 2:
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write_c0_watchlo1(watches->watchlo[1]);
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write_c0_watchlo1(watches->watchlo[1]);
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write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
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write_c0_watchhi1(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
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watches->watchhi[1]);
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case 1:
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case 1:
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write_c0_watchlo0(watches->watchlo[0]);
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write_c0_watchlo0(watches->watchlo[0]);
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write_c0_watchhi0(0x40000007 | watches->watchhi[0]);
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write_c0_watchhi0(MIPS_WATCHHI_G | MIPS_WATCHHI_IRW |
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watches->watchhi[0]);
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}
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}
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}
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}
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@ -51,22 +55,26 @@ void mips_read_watch_registers(void)
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default:
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default:
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BUG();
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BUG();
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case 4:
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case 4:
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watches->watchhi[3] = (read_c0_watchhi3() & 0x0fff);
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watches->watchhi[3] = (read_c0_watchhi3() &
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(MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
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case 3:
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case 3:
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watches->watchhi[2] = (read_c0_watchhi2() & 0x0fff);
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watches->watchhi[2] = (read_c0_watchhi2() &
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(MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
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case 2:
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case 2:
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watches->watchhi[1] = (read_c0_watchhi1() & 0x0fff);
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watches->watchhi[1] = (read_c0_watchhi1() &
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(MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
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case 1:
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case 1:
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watches->watchhi[0] = (read_c0_watchhi0() & 0x0fff);
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watches->watchhi[0] = (read_c0_watchhi0() &
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(MIPS_WATCHHI_MASK | MIPS_WATCHHI_IRW));
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}
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}
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if (current_cpu_data.watch_reg_use_cnt == 1 &&
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if (current_cpu_data.watch_reg_use_cnt == 1 &&
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(watches->watchhi[0] & 7) == 0) {
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(watches->watchhi[0] & MIPS_WATCHHI_IRW) == 0) {
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/* Pathological case of release 1 architecture that
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/* Pathological case of release 1 architecture that
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* doesn't set the condition bits. We assume that
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* doesn't set the condition bits. We assume that
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* since we got here, the watch condition was met and
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* since we got here, the watch condition was met and
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* signal that the conditions requested in watchlo
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* signal that the conditions requested in watchlo
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* were met. */
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* were met. */
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watches->watchhi[0] |= (watches->watchlo[0] & 7);
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watches->watchhi[0] |= (watches->watchlo[0] & MIPS_WATCHHI_IRW);
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}
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}
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}
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}
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@ -109,86 +117,86 @@ void mips_probe_watch_registers(struct cpuinfo_mips *c)
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* Check which of the I,R and W bits are supported, then
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* Check which of the I,R and W bits are supported, then
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* disable the register.
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* disable the register.
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*/
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*/
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write_c0_watchlo0(7);
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write_c0_watchlo0(MIPS_WATCHLO_IRW);
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back_to_back_c0_hazard();
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back_to_back_c0_hazard();
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t = read_c0_watchlo0();
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t = read_c0_watchlo0();
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write_c0_watchlo0(0);
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write_c0_watchlo0(0);
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c->watch_reg_masks[0] = t & 7;
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c->watch_reg_masks[0] = t & MIPS_WATCHLO_IRW;
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/* Write the mask bits and read them back to determine which
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/* Write the mask bits and read them back to determine which
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* can be used. */
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* can be used. */
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c->watch_reg_count = 1;
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c->watch_reg_count = 1;
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c->watch_reg_use_cnt = 1;
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c->watch_reg_use_cnt = 1;
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t = read_c0_watchhi0();
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t = read_c0_watchhi0();
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write_c0_watchhi0(t | 0xff8);
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write_c0_watchhi0(t | MIPS_WATCHHI_MASK);
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back_to_back_c0_hazard();
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back_to_back_c0_hazard();
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t = read_c0_watchhi0();
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t = read_c0_watchhi0();
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c->watch_reg_masks[0] |= (t & 0xff8);
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c->watch_reg_masks[0] |= (t & MIPS_WATCHHI_MASK);
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if ((t & 0x80000000) == 0)
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if ((t & MIPS_WATCHHI_M) == 0)
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return;
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return;
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write_c0_watchlo1(7);
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write_c0_watchlo1(MIPS_WATCHLO_IRW);
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back_to_back_c0_hazard();
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back_to_back_c0_hazard();
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t = read_c0_watchlo1();
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t = read_c0_watchlo1();
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write_c0_watchlo1(0);
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write_c0_watchlo1(0);
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c->watch_reg_masks[1] = t & 7;
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c->watch_reg_masks[1] = t & MIPS_WATCHLO_IRW;
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c->watch_reg_count = 2;
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c->watch_reg_count = 2;
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c->watch_reg_use_cnt = 2;
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c->watch_reg_use_cnt = 2;
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t = read_c0_watchhi1();
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t = read_c0_watchhi1();
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write_c0_watchhi1(t | 0xff8);
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write_c0_watchhi1(t | MIPS_WATCHHI_MASK);
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back_to_back_c0_hazard();
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back_to_back_c0_hazard();
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t = read_c0_watchhi1();
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t = read_c0_watchhi1();
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c->watch_reg_masks[1] |= (t & 0xff8);
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c->watch_reg_masks[1] |= (t & MIPS_WATCHHI_MASK);
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if ((t & 0x80000000) == 0)
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if ((t & MIPS_WATCHHI_M) == 0)
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return;
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return;
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write_c0_watchlo2(7);
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write_c0_watchlo2(MIPS_WATCHLO_IRW);
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back_to_back_c0_hazard();
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back_to_back_c0_hazard();
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t = read_c0_watchlo2();
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t = read_c0_watchlo2();
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write_c0_watchlo2(0);
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write_c0_watchlo2(0);
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c->watch_reg_masks[2] = t & 7;
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c->watch_reg_masks[2] = t & MIPS_WATCHLO_IRW;
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c->watch_reg_count = 3;
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c->watch_reg_count = 3;
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c->watch_reg_use_cnt = 3;
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c->watch_reg_use_cnt = 3;
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t = read_c0_watchhi2();
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t = read_c0_watchhi2();
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write_c0_watchhi2(t | 0xff8);
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write_c0_watchhi2(t | MIPS_WATCHHI_MASK);
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back_to_back_c0_hazard();
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back_to_back_c0_hazard();
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t = read_c0_watchhi2();
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t = read_c0_watchhi2();
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c->watch_reg_masks[2] |= (t & 0xff8);
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c->watch_reg_masks[2] |= (t & MIPS_WATCHHI_MASK);
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if ((t & 0x80000000) == 0)
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if ((t & MIPS_WATCHHI_M) == 0)
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return;
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return;
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write_c0_watchlo3(7);
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write_c0_watchlo3(MIPS_WATCHLO_IRW);
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back_to_back_c0_hazard();
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back_to_back_c0_hazard();
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t = read_c0_watchlo3();
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t = read_c0_watchlo3();
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write_c0_watchlo3(0);
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write_c0_watchlo3(0);
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c->watch_reg_masks[3] = t & 7;
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c->watch_reg_masks[3] = t & MIPS_WATCHLO_IRW;
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c->watch_reg_count = 4;
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c->watch_reg_count = 4;
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c->watch_reg_use_cnt = 4;
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c->watch_reg_use_cnt = 4;
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t = read_c0_watchhi3();
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t = read_c0_watchhi3();
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write_c0_watchhi3(t | 0xff8);
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write_c0_watchhi3(t | MIPS_WATCHHI_MASK);
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back_to_back_c0_hazard();
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back_to_back_c0_hazard();
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t = read_c0_watchhi3();
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t = read_c0_watchhi3();
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c->watch_reg_masks[3] |= (t & 0xff8);
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c->watch_reg_masks[3] |= (t & MIPS_WATCHHI_MASK);
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if ((t & 0x80000000) == 0)
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if ((t & MIPS_WATCHHI_M) == 0)
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return;
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return;
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/* We use at most 4, but probe and report up to 8. */
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/* We use at most 4, but probe and report up to 8. */
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c->watch_reg_count = 5;
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c->watch_reg_count = 5;
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t = read_c0_watchhi4();
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t = read_c0_watchhi4();
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if ((t & 0x80000000) == 0)
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if ((t & MIPS_WATCHHI_M) == 0)
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return;
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return;
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c->watch_reg_count = 6;
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c->watch_reg_count = 6;
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t = read_c0_watchhi5();
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t = read_c0_watchhi5();
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if ((t & 0x80000000) == 0)
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if ((t & MIPS_WATCHHI_M) == 0)
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return;
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return;
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c->watch_reg_count = 7;
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c->watch_reg_count = 7;
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t = read_c0_watchhi6();
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t = read_c0_watchhi6();
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if ((t & 0x80000000) == 0)
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if ((t & MIPS_WATCHHI_M) == 0)
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return;
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return;
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c->watch_reg_count = 8;
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c->watch_reg_count = 8;
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