drm/radeon: clean up active vram sizing
If we are not able to properly initialize one of the gpu engines for buffer paging, we limit vram to the size of the cpu visible aperture. We generally either use the gfx or dma engine to do this. Clean up the size limiting code to only adjust the size based on what ring is selected for buffer paging rather than making assumptions about which engine is selected for paging. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com>
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@ -3840,6 +3840,8 @@ static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
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if (enable)
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if (enable)
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WREG32(CP_ME_CNTL, 0);
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WREG32(CP_ME_CNTL, 0);
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else {
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else {
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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}
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}
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@ -4038,6 +4040,10 @@ static int cik_cp_gfx_resume(struct radeon_device *rdev)
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
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return r;
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return r;
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}
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}
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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return 0;
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}
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}
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@ -250,6 +250,8 @@ static void cik_sdma_gfx_stop(struct radeon_device *rdev)
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u32 rb_cntl, reg_offset;
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u32 rb_cntl, reg_offset;
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int i;
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int i;
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if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
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(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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for (i = 0; i < 2; i++) {
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for (i = 0; i < 2; i++) {
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@ -381,6 +383,8 @@ static int cik_sdma_gfx_resume(struct radeon_device *rdev)
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}
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}
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}
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}
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if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
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(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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return 0;
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@ -1390,6 +1390,7 @@ static void cayman_cp_enable(struct radeon_device *rdev, bool enable)
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if (enable)
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if (enable)
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WREG32(CP_ME_CNTL, 0);
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WREG32(CP_ME_CNTL, 0);
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else {
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else {
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
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WREG32(SCRATCH_UMSK, 0);
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WREG32(SCRATCH_UMSK, 0);
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@ -1663,6 +1664,9 @@ static int cayman_cp_resume(struct radeon_device *rdev)
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return r;
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return r;
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}
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}
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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return 0;
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}
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}
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@ -157,6 +157,8 @@ void cayman_dma_stop(struct radeon_device *rdev)
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{
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{
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u32 rb_cntl;
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u32 rb_cntl;
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if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
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(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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/* dma0 */
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/* dma0 */
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@ -259,6 +261,8 @@ int cayman_dma_resume(struct radeon_device *rdev)
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}
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}
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}
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}
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if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
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(rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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return 0;
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@ -2254,6 +2254,7 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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*/
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*/
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void r600_cp_stop(struct radeon_device *rdev)
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void r600_cp_stop(struct radeon_device *rdev)
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{
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{
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
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WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
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WREG32(SCRATCH_UMSK, 0);
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WREG32(SCRATCH_UMSK, 0);
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@ -2613,8 +2614,7 @@ int r600_cp_resume(struct radeon_device *rdev)
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return r;
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return r;
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}
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}
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/* RV7xx+ uses dma for paging */
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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if (rdev->family < CHIP_RV770)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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return 0;
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@ -100,6 +100,7 @@ void r600_dma_stop(struct radeon_device *rdev)
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{
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{
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u32 rb_cntl = RREG32(DMA_RB_CNTL);
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u32 rb_cntl = RREG32(DMA_RB_CNTL);
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if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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rb_cntl &= ~DMA_RB_ENABLE;
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rb_cntl &= ~DMA_RB_ENABLE;
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@ -187,6 +188,7 @@ int r600_dma_resume(struct radeon_device *rdev)
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return r;
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return r;
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}
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}
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if (rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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return 0;
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@ -1071,6 +1071,7 @@ static void rv770_mc_program(struct radeon_device *rdev)
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*/
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*/
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void r700_cp_stop(struct radeon_device *rdev)
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void r700_cp_stop(struct radeon_device *rdev)
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{
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{
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
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WREG32(SCRATCH_UMSK, 0);
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WREG32(SCRATCH_UMSK, 0);
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@ -3249,6 +3249,7 @@ static void si_cp_enable(struct radeon_device *rdev, bool enable)
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if (enable)
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if (enable)
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WREG32(CP_ME_CNTL, 0);
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WREG32(CP_ME_CNTL, 0);
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else {
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else {
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
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WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
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WREG32(SCRATCH_UMSK, 0);
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WREG32(SCRATCH_UMSK, 0);
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@ -3510,6 +3511,9 @@ static int si_cp_resume(struct radeon_device *rdev)
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si_enable_gui_idle_interrupt(rdev, true);
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si_enable_gui_idle_interrupt(rdev, true);
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if (rdev->asic->copy.copy_ring_index == RADEON_RING_TYPE_GFX_INDEX)
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radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
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return 0;
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return 0;
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}
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}
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