dt-bindings: mediatek: Add binding for mt2712 IOMMU and SMI
This patch adds decriptions for mt2712 IOMMU and SMI.
In order to balance the bandwidth, mt2712 has two M4Us, two
smi-commons, 10 smi-larbs. and mt2712 is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt2712 M4U-SMI HW diagram is as below:
EMI
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------------------------------------
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M4U0 M4U1
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smi-common0 smi-common1
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------------------------- --------------------------------
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larb0 larb1 larb2 larb3 larb6 larb4 larb5 larb7 larb8 larb9
disp0 vdec cam venc jpg mdp1/disp1 mdp2/disp2 mdp3 vdo/nr tvd
All the connections are HW fixed, SW can NOT adjust it.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Yong Wu
Matthias Brugger
parent
2b519747ae
commit
50fa3cd33f
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@ -40,6 +40,7 @@ video decode local arbiter, all these ports are according to the video HW.
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Required properties:
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- compatible : must be one of the following string:
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"mediatek,mt2701-m4u" for mt2701 which uses generation one m4u HW.
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"mediatek,mt2712-m4u" for mt2712 which uses generation two m4u HW.
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"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
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- reg : m4u register base and size.
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- interrupts : the interrupt of m4u.
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@ -50,8 +51,9 @@ Required properties:
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according to the local arbiter index, like larb0, larb1, larb2...
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- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
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Specifies the mtk_m4u_id as defined in
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dt-binding/memory/mt2701-larb-port.h for mt2701 and
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dt-binding/memory/mt8173-larb-port.h for mt8173
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dt-binding/memory/mt2701-larb-port.h for mt2701,
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dt-binding/memory/mt2712-larb-port.h for mt2712, and
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dt-binding/memory/mt8173-larb-port.h for mt8173.
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Example:
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iommu: iommu@10205000 {
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@ -2,8 +2,9 @@ SMI (Smart Multimedia Interface) Common
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The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
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Mediatek SMI have two generations of HW architecture, mt8173 uses the second
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generation of SMI HW while mt2701 uses the first generation HW of SMI.
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Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use
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the second generation of SMI HW while mt2701 uses the first generation HW of
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SMI.
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There's slight differences between the two SMI, for generation 2, the
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register which control the iommu port is at each larb's register base. But
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@ -15,6 +16,7 @@ not needed for SMI generation 2.
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Required properties:
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- compatible : must be one of :
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"mediatek,mt2701-smi-common"
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"mediatek,mt2712-smi-common"
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"mediatek,mt8173-smi-common"
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- reg : the register and size of the SMI block.
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- power-domains : a phandle to the power domain of this local arbiter.
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@ -4,8 +4,9 @@ The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
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Required properties:
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- compatible : must be one of :
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"mediatek,mt8173-smi-larb"
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"mediatek,mt2701-smi-larb"
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"mediatek,mt2712-smi-larb"
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"mediatek,mt8173-smi-larb"
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- reg : the register and size of this local arbiter.
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- mediatek,smi : a phandle to the smi_common node.
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- power-domains : a phandle to the power domain of this local arbiter.
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@ -15,7 +16,7 @@ Required properties:
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the register.
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- "smi" : It's the clock for transfer data and command.
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Required property for mt2701:
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Required property for mt2701 and mt2712:
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- mediatek,larb-id :the hardware id of this larb.
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Example:
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@ -0,0 +1,95 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2017 MediaTek Inc.
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* Author: Yong Wu <yong.wu@mediatek.com>
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*/
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#ifndef __DTS_IOMMU_PORT_MT2712_H
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#define __DTS_IOMMU_PORT_MT2712_H
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#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
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#define M4U_LARB0_ID 0
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#define M4U_LARB1_ID 1
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#define M4U_LARB2_ID 2
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#define M4U_LARB3_ID 3
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#define M4U_LARB4_ID 4
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#define M4U_LARB5_ID 5
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#define M4U_LARB6_ID 6
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#define M4U_LARB7_ID 7
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#define M4U_LARB8_ID 8
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#define M4U_LARB9_ID 9
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/* larb0 */
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#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
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#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
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#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
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#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
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#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
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#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
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#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
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#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB0_ID, 7)
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/* larb1 */
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#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
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#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
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#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
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#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
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#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
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#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
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#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
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#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7)
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#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8)
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#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9)
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#define M4U_PORT_HW_IMG_RESZ_EXT MTK_M4U_ID(M4U_LARB1_ID, 10)
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/* larb2 */
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#define M4U_PORT_CAM_DMA0 MTK_M4U_ID(M4U_LARB2_ID, 0)
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#define M4U_PORT_CAM_DMA1 MTK_M4U_ID(M4U_LARB2_ID, 1)
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#define M4U_PORT_CAM_DMA2 MTK_M4U_ID(M4U_LARB2_ID, 2)
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/* larb3 */
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#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)
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#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)
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#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)
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#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)
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#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)
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#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 5)
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#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 6)
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#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 7)
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#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 8)
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/* larb4 */
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#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0)
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#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1)
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#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 2)
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#define M4U_PORT_DISP_OD1_R MTK_M4U_ID(M4U_LARB4_ID, 3)
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#define M4U_PORT_DISP_OD1_W MTK_M4U_ID(M4U_LARB4_ID, 4)
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#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 5)
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#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 6)
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/* larb5 */
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#define M4U_PORT_DISP_OVL2 MTK_M4U_ID(M4U_LARB5_ID, 0)
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#define M4U_PORT_DISP_WDMA2 MTK_M4U_ID(M4U_LARB5_ID, 1)
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#define M4U_PORT_MDP_RDMA2 MTK_M4U_ID(M4U_LARB5_ID, 2)
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#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB5_ID, 3)
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/* larb6 */
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#define M4U_PORT_JPGDEC_WDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 0)
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#define M4U_PORT_JPGDEC_WDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 1)
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#define M4U_PORT_JPGDEC_BSDMA_0 MTK_M4U_ID(M4U_LARB6_ID, 2)
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#define M4U_PORT_JPGDEC_BSDMA_1 MTK_M4U_ID(M4U_LARB6_ID, 3)
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/* larb7 */
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#define M4U_PORT_MDP_RDMA3 MTK_M4U_ID(M4U_LARB7_ID, 0)
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#define M4U_PORT_MDP_WROT2 MTK_M4U_ID(M4U_LARB7_ID, 1)
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/* larb8 */
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#define M4U_PORT_VDO MTK_M4U_ID(M4U_LARB8_ID, 0)
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#define M4U_PORT_NR MTK_M4U_ID(M4U_LARB8_ID, 1)
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#define M4U_PORT_WR_CHANNEL0 MTK_M4U_ID(M4U_LARB8_ID, 2)
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/* larb9 */
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#define M4U_PORT_TVD MTK_M4U_ID(M4U_LARB9_ID, 0)
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#define M4U_PORT_WR_CHANNEL1 MTK_M4U_ID(M4U_LARB9_ID, 1)
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#endif
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