Merge master.kernel.org:/pub/scm/linux/kernel/git/aegl/linux-2.6
This commit is contained in:
commit
514fd7fd01
|
@ -220,13 +220,6 @@ config IOSAPIC
|
|||
depends on !IA64_HP_SIM
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default y
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config IA64_SGI_SN_SIM
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bool "SGI Medusa Simulator Support"
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||||
depends on IA64_SGI_SN2 || IA64_GENERIC
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||||
help
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||||
If you are compiling a kernel that will run under SGI's IA-64
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||||
simulator (Medusa) then say Y, otherwise say N.
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||||
config IA64_SGI_SN_XP
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tristate "Support communication between SGI SSIs"
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select IA64_UNCACHED_ALLOCATOR
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|
|
|
@ -81,7 +81,6 @@ CONFIG_HOLES_IN_ZONE=y
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CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
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# CONFIG_IA64_CYCLONE is not set
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CONFIG_IOSAPIC=y
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CONFIG_IA64_SGI_SN_SIM=y
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CONFIG_FORCE_MAX_ZONEORDER=18
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CONFIG_SMP=y
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CONFIG_NR_CPUS=512
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|
|
|
@ -20,6 +20,7 @@
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* 02/01/00 R.Seth fixed get_cpuinfo for SMP
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* 01/07/99 S.Eranian added the support for command line argument
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* 06/24/99 W.Drummond added boot_cpu_data.
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* 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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|
@ -84,6 +85,13 @@ struct io_space io_space[MAX_IO_SPACES];
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EXPORT_SYMBOL(io_space);
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unsigned int num_io_spaces;
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/*
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* "flush_icache_range()" needs to know what processor dependent stride size to use
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* when it makes i-cache(s) coherent with d-caches.
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*/
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#define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
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unsigned long ia64_i_cache_stride_shift = ~0;
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/*
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* The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
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* mask specifies a mask of address bits that must be 0 in order for two buffers to be
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|
@ -628,6 +636,12 @@ setup_per_cpu_areas (void)
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/* start_kernel() requires this... */
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}
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/*
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* Calculate the max. cache line size.
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*
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* In addition, the minimum of the i-cache stride sizes is calculated for
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* "flush_icache_range()".
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*/
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static void
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get_max_cacheline_size (void)
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{
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|
@ -641,6 +655,8 @@ get_max_cacheline_size (void)
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printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
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__FUNCTION__, status);
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max = SMP_CACHE_BYTES;
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/* Safest setup for "flush_icache_range()" */
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ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
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goto out;
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}
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@ -649,14 +665,31 @@ get_max_cacheline_size (void)
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&cci);
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if (status != 0) {
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printk(KERN_ERR
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"%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
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"%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
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__FUNCTION__, l, status);
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max = SMP_CACHE_BYTES;
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/* The safest setup for "flush_icache_range()" */
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cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
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cci.pcci_unified = 1;
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}
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line_size = 1 << cci.pcci_line_size;
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if (line_size > max)
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max = line_size;
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}
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if (!cci.pcci_unified) {
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status = ia64_pal_cache_config_info(l,
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/* cache_type (instruction)= */ 1,
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&cci);
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if (status != 0) {
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printk(KERN_ERR
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"%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
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__FUNCTION__, l, status);
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/* The safest setup for "flush_icache_range()" */
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cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
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}
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}
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if (cci.pcci_stride < ia64_i_cache_stride_shift)
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ia64_i_cache_stride_shift = cci.pcci_stride;
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||||
}
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out:
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if (max > ia64_max_cacheline_size)
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ia64_max_cacheline_size = max;
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|
|
|
@ -3,37 +3,59 @@
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*
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* Copyright (C) 1999-2001, 2005 Hewlett-Packard Co
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* David Mosberger-Tang <davidm@hpl.hp.com>
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*
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* 05/28/05 Zoltan Menyhart Dynamic stride size
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*/
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#include <asm/asmmacro.h>
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#include <asm/page.h>
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/*
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* flush_icache_range(start,end)
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* Must flush range from start to end-1 but nothing else (need to
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*
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* Make i-cache(s) coherent with d-caches.
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*
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* Must deal with range from start to end-1 but nothing else (need to
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* be careful not to touch addresses that may be unmapped).
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*
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* Note: "in0" and "in1" are preserved for debugging purposes.
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*/
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GLOBAL_ENTRY(flush_icache_range)
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.prologue
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alloc r2=ar.pfs,2,0,0,0
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sub r8=in1,in0,1
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alloc r2=ar.pfs,2,0,0,0
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movl r3=ia64_i_cache_stride_shift
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mov r21=1
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;;
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shr.u r8=r8,5 // we flush 32 bytes per iteration
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.save ar.lc, r3
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mov r3=ar.lc // save ar.lc
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ld8 r20=[r3] // r20: stride shift
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sub r22=in1,r0,1 // last byte address
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;;
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shr.u r23=in0,r20 // start / (stride size)
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shr.u r22=r22,r20 // (last byte address) / (stride size)
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shl r21=r21,r20 // r21: stride size of the i-cache(s)
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;;
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sub r8=r22,r23 // number of strides - 1
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shl r24=r23,r20 // r24: addresses for "fc.i" =
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// "start" rounded down to stride boundary
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.save ar.lc,r3
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mov r3=ar.lc // save ar.lc
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;;
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.body
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mov ar.lc=r8
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||||
mov ar.lc=r8
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;;
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.Loop: fc.i in0 // issuable on M2 only
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||||
add in0=32,in0
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||||
/*
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* 32 byte aligned loop, even number of (actually 2) bundles
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||||
*/
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.Loop: fc.i r24 // issuable on M0 only
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add r24=r21,r24 // we flush "stride size" bytes per iteration
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nop.i 0
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||||
br.cloop.sptk.few .Loop
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;;
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sync.i
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;;
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srlz.i
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;;
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mov ar.lc=r3 // restore ar.lc
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mov ar.lc=r3 // restore ar.lc
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br.ret.sptk.many rp
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END(flush_icache_range)
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|
|
|
@ -157,6 +157,7 @@ alloc_pci_controller (int seg)
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|||
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||||
memset(controller, 0, sizeof(*controller));
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controller->segment = seg;
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controller->node = -1;
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return controller;
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}
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|
@ -288,6 +289,7 @@ pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
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unsigned int windows = 0;
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struct pci_bus *pbus;
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char *name;
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int pxm;
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controller = alloc_pci_controller(domain);
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if (!controller)
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|
@ -295,10 +297,16 @@ pci_acpi_scan_root(struct acpi_device *device, int domain, int bus)
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|
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controller->acpi_handle = device->handle;
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pxm = acpi_get_pxm(controller->acpi_handle);
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#ifdef CONFIG_NUMA
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if (pxm >= 0)
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controller->node = pxm_to_nid_map[pxm];
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#endif
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acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
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&windows);
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controller->window = kmalloc(sizeof(*controller->window) * windows,
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GFP_KERNEL);
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controller->window = kmalloc_node(sizeof(*controller->window) * windows,
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GFP_KERNEL, controller->node);
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if (!controller->window)
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goto out2;
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|
|
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@ -61,7 +61,7 @@ sn_default_pci_unmap(struct pci_dev *pdev, dma_addr_t addr, int direction)
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}
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static void *
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sn_default_pci_bus_fixup(struct pcibus_bussoft *soft)
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sn_default_pci_bus_fixup(struct pcibus_bussoft *soft, struct pci_controller *controller)
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{
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return NULL;
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}
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|
@ -362,7 +362,7 @@ void sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
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provider_soft = NULL;
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if (provider->bus_fixup)
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provider_soft = (*provider->bus_fixup) (prom_bussoft_ptr);
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provider_soft = (*provider->bus_fixup) (prom_bussoft_ptr, controller);
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if (provider_soft == NULL)
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return; /* fixup failed or not applicable */
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|
@ -380,6 +380,22 @@ void sn_pci_controller_fixup(int segment, int busnum, struct pci_bus *bus)
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SN_PCIBUS_BUSSOFT(bus)->bs_xwidget_info =
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&(hubdev_info->hdi_xwidget_info[SN_PCIBUS_BUSSOFT(bus)->bs_xid]);
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/*
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* If the node information we obtained during the fixup phase is invalid
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* then set controller->node to -1 (undetermined)
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*/
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if (controller->node >= num_online_nodes()) {
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struct pcibus_bussoft *b = SN_PCIBUS_BUSSOFT(bus);
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printk(KERN_WARNING "Device ASIC=%u XID=%u PBUSNUM=%lu"
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"L_IO=%lx L_MEM=%lx BASE=%lx\n",
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b->bs_asic_type, b->bs_xid, b->bs_persist_busnum,
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b->bs_legacy_io, b->bs_legacy_mem, b->bs_base);
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printk(KERN_WARNING "on node %d but only %d nodes online."
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"Association set to undetermined.\n",
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controller->node, num_online_nodes());
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controller->node = -1;
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}
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return;
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error_return:
|
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|
|
|
@ -72,7 +72,7 @@ xpc_initialize_channels(struct xpc_partition *part, partid_t partid)
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|||
enum xpc_retval
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xpc_setup_infrastructure(struct xpc_partition *part)
|
||||
{
|
||||
int ret;
|
||||
int ret, cpuid;
|
||||
struct timer_list *timer;
|
||||
partid_t partid = XPC_PARTID(part);
|
||||
|
||||
|
@ -223,9 +223,9 @@ xpc_setup_infrastructure(struct xpc_partition *part)
|
|||
xpc_vars_part[partid].openclose_args_pa =
|
||||
__pa(part->local_openclose_args);
|
||||
xpc_vars_part[partid].IPI_amo_pa = __pa(part->local_IPI_amo_va);
|
||||
xpc_vars_part[partid].IPI_nasid = cpuid_to_nasid(smp_processor_id());
|
||||
xpc_vars_part[partid].IPI_phys_cpuid =
|
||||
cpu_physical_id(smp_processor_id());
|
||||
cpuid = raw_smp_processor_id(); /* any CPU in this partition will do */
|
||||
xpc_vars_part[partid].IPI_nasid = cpuid_to_nasid(cpuid);
|
||||
xpc_vars_part[partid].IPI_phys_cpuid = cpu_physical_id(cpuid);
|
||||
xpc_vars_part[partid].nchannels = part->nchannels;
|
||||
xpc_vars_part[partid].magic = XPC_VP_MAGIC1;
|
||||
|
||||
|
|
|
@ -79,6 +79,7 @@ void *sn_dma_alloc_coherent(struct device *dev, size_t size,
|
|||
{
|
||||
void *cpuaddr;
|
||||
unsigned long phys_addr;
|
||||
int node;
|
||||
struct pci_dev *pdev = to_pci_dev(dev);
|
||||
struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
|
||||
|
||||
|
@ -86,10 +87,19 @@ void *sn_dma_alloc_coherent(struct device *dev, size_t size,
|
|||
|
||||
/*
|
||||
* Allocate the memory.
|
||||
* FIXME: We should be doing alloc_pages_node for the node closest
|
||||
* to the PCI device.
|
||||
*/
|
||||
if (!(cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size))))
|
||||
node = pcibus_to_node(pdev->bus);
|
||||
if (likely(node >=0)) {
|
||||
struct page *p = alloc_pages_node(node, GFP_ATOMIC, get_order(size));
|
||||
|
||||
if (likely(p))
|
||||
cpuaddr = page_address(p);
|
||||
else
|
||||
return NULL;
|
||||
} else
|
||||
cpuaddr = (void *)__get_free_pages(GFP_ATOMIC, get_order(size));
|
||||
|
||||
if (unlikely(!cpuaddr))
|
||||
return NULL;
|
||||
|
||||
memset(cpuaddr, 0x0, size);
|
||||
|
|
|
@ -85,7 +85,7 @@ pcibr_error_intr_handler(int irq, void *arg, struct pt_regs *regs)
|
|||
}
|
||||
|
||||
void *
|
||||
pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft)
|
||||
pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
|
||||
{
|
||||
int nasid, cnode, j;
|
||||
struct hubdev_info *hubdev_info;
|
||||
|
@ -158,6 +158,14 @@ pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft)
|
|||
memset(soft->pbi_int_ate_resource.ate, 0,
|
||||
(soft->pbi_int_ate_size * sizeof(uint64_t)));
|
||||
|
||||
if (prom_bussoft->bs_asic_type == PCIIO_ASIC_TYPE_TIOCP)
|
||||
/*
|
||||
* TIO PCI Bridge with no closest node information.
|
||||
* FIXME: Find another way to determine the closest node
|
||||
*/
|
||||
controller->node = -1;
|
||||
else
|
||||
controller->node = cnode;
|
||||
return soft;
|
||||
}
|
||||
|
||||
|
|
|
@ -581,7 +581,7 @@ tioca_error_intr_handler(int irq, void *arg, struct pt_regs *pt)
|
|||
* the caller.
|
||||
*/
|
||||
static void *
|
||||
tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft)
|
||||
tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller)
|
||||
{
|
||||
struct tioca_common *tioca_common;
|
||||
struct tioca_kernel *tioca_kern;
|
||||
|
@ -646,6 +646,8 @@ tioca_bus_fixup(struct pcibus_bussoft *prom_bussoft)
|
|||
__FUNCTION__, SGI_TIOCA_ERROR,
|
||||
(int)tioca_common->ca_common.bs_persist_busnum);
|
||||
|
||||
/* Setup locality information */
|
||||
controller->node = tioca_kern->ca_closest_node;
|
||||
return tioca_common;
|
||||
}
|
||||
|
||||
|
|
|
@ -52,6 +52,8 @@ struct pcdp_uart {
|
|||
u32 clock_rate;
|
||||
u8 pci_prog_intfc;
|
||||
u8 flags;
|
||||
u16 conout_index;
|
||||
u32 reserved;
|
||||
} __attribute__((packed));
|
||||
|
||||
#define PCDP_IF_PCI 1
|
||||
|
|
|
@ -128,6 +128,7 @@ struct pci_controller {
|
|||
void *acpi_handle;
|
||||
void *iommu;
|
||||
int segment;
|
||||
int node; /* nearest node with memory or -1 for global allocation */
|
||||
|
||||
unsigned int windows;
|
||||
struct pci_window *window;
|
||||
|
|
|
@ -128,7 +128,7 @@ pcibr_lock(struct pcibus_info *pcibus_info)
|
|||
#define pcibr_unlock(pcibus_info, flag) spin_unlock_irqrestore(&pcibus_info->pbi_lock, flag)
|
||||
|
||||
extern int pcibr_init_provider(void);
|
||||
extern void *pcibr_bus_fixup(struct pcibus_bussoft *);
|
||||
extern void *pcibr_bus_fixup(struct pcibus_bussoft *, struct pci_controller *);
|
||||
extern dma_addr_t pcibr_dma_map(struct pci_dev *, unsigned long, size_t);
|
||||
extern dma_addr_t pcibr_dma_map_consistent(struct pci_dev *, unsigned long, size_t);
|
||||
extern void pcibr_dma_unmap(struct pci_dev *, dma_addr_t, int);
|
||||
|
|
|
@ -37,6 +37,7 @@ struct pcibus_bussoft {
|
|||
struct xwidget_info *bs_xwidget_info;
|
||||
};
|
||||
|
||||
struct pci_controller;
|
||||
/*
|
||||
* SN pci bus indirection
|
||||
*/
|
||||
|
@ -45,7 +46,7 @@ struct sn_pcibus_provider {
|
|||
dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t);
|
||||
dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t);
|
||||
void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
|
||||
void * (*bus_fixup)(struct pcibus_bussoft *);
|
||||
void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
|
||||
};
|
||||
|
||||
extern struct sn_pcibus_provider *sn_pci_provider[];
|
||||
|
|
|
@ -13,16 +13,9 @@
|
|||
#define SNMAGIC 0xaeeeeeee8badbeefL
|
||||
#define IS_MEDUSA() ({long sn; asm("mov %0=cpuid[%1]" : "=r"(sn) : "r"(2)); sn == SNMAGIC;})
|
||||
|
||||
#ifdef CONFIG_IA64_SGI_SN_SIM
|
||||
#define SIMULATOR_SLEEP() asm("nop.i 0x8beef")
|
||||
#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
|
||||
#define IS_RUNNING_ON_SIMULATOR() (sn_prom_type)
|
||||
#define IS_RUNNING_ON_FAKE_PROM() (sn_prom_type == 2)
|
||||
extern int sn_prom_type; /* 0=hardware, 1=medusa/realprom, 2=medusa/fakeprom */
|
||||
#else
|
||||
#define IS_RUNNING_ON_SIMULATOR() (0)
|
||||
#define IS_RUNNING_ON_FAKE_PROM() (0)
|
||||
#define SIMULATOR_SLEEP()
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* _ASM_IA64_SN_SIMULATOR_H */
|
||||
|
|
|
@ -40,6 +40,11 @@
|
|||
*/
|
||||
#define node_to_first_cpu(node) (__ffs(node_to_cpumask(node)))
|
||||
|
||||
/*
|
||||
* Determines the node for a given pci bus
|
||||
*/
|
||||
#define pcibus_to_node(bus) PCI_CONTROLLER(bus)->node
|
||||
|
||||
void build_cpu_to_node_map(void);
|
||||
|
||||
#define SD_CPU_INIT (struct sched_domain) { \
|
||||
|
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Loading…
Reference in New Issue