clk: tegra: Changes for v5.10-rc1
This is a set of small fixes for the Tegra clock driver. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEiOrDCAFJzPfAjcif3SOs138+s6EFAl9omSgTHHRyZWRpbmdA bnZpZGlhLmNvbQAKCRDdI6zXfz6zoWoDD/9ZPdwNxZEo9w6dtARvfWHuauvo0IVy xPSHbuY+7Wl4SYu5p8Ccw2zqR80JKW+77P3BIC4P0YP58hCs6LvdlrQapwHi2do2 5tfLCcst5tlf5EDdugmtj/E7NApQbOCcgq6DCREGjK9BNbngBGowhOX+0ECMQQaR RXKNYZGmOmLCqoy0CxwIEhem9HMRKVKAMlJF5aBEJTZHzm/BWhInpDr3Hh5Yp1cq Br0s6Z6FRLwblgohMQQ9KwprVG80/8RO3wn57aNjs9Tna7Q9KtDRTcqUeLKVphlu +KIp4gEDp88Ej/2lprcu0mmnVXVCQDqxxNqxWfNVqZZou/EWS8yW4+dHRYDVttZ2 19UJIzr6Q5UIip12MN10GjPYBjTzzw+M9avoxSdVuErakBmJJ+D37XG4HzGzcfCU mtZN7fHRFZH5TeVL3yFkN3oVlFVZAIMM1iccTwt/D2cWltXDTLZjLGbDxcO+qL2U VOBZG28o7a1qrvkcpSUMSnVH+ApapmXMZLcnA6Rp2yECJUDIIowSpTI5CTfuhK5b C7vNX8L7n3mXmmQlQVblxmrU6htX+Zp2hFLtA3x/Pgbt+wFT+CxYE75Jf/mJLJRK OH20dCMjDOMz/d6d2ThKnMEJSSnOTEj81XVlKzvUxceiB6AQvN1eodr5sTXHin1W ujB3Q7zyvWVlrQ== =oT14 -----END PGP SIGNATURE----- Merge tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes Pull Tegra clk driver fixes from Thierry Reding: This is a set of small fixes for the Tegra clock driver. * tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: Fix missing prototype for tegra210_clk_register_emc() clk: tegra: Always program PLL_E when enabled clk: tegra: Capitalization fixes
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commit
51644df867
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@ -1611,9 +1611,6 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
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unsigned long flags = 0;
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unsigned long input_rate;
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if (clk_pll_is_enabled(hw))
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return 0;
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input_rate = clk_hw_get_rate(clk_hw_get_parent(hw));
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if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))
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@ -1673,7 +1670,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
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pll_writel(val, PLLE_SS_CTRL, pll);
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udelay(1);
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/* Enable hw control of xusb brick pll */
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/* Enable HW control of XUSB brick PLL */
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val = pll_readl_misc(pll);
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val &= ~PLLE_MISC_IDDQ_SW_CTRL;
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pll_writel_misc(val, pll);
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@ -1696,7 +1693,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw)
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val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
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pll_writel(val, XUSBIO_PLL_CFG0, pll);
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/* Enable hw control of SATA pll */
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/* Enable HW control of SATA PLL */
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val = pll_readl(SATA_PLL_CFG0, pll);
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val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;
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val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;
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@ -12,6 +12,8 @@
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#include <linux/io.h>
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#include <linux/slab.h>
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#include "clk.h"
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#define CLK_SOURCE_EMC 0x19c
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#define CLK_SOURCE_EMC_2X_CLK_SRC GENMASK(31, 29)
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#define CLK_SOURCE_EMC_MC_EMC_SAME_FREQ BIT(16)
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