s390: add support to start the kernel in 64 bit mode.
Do the switch to z/Architecture (alias 64 bit) mode early in head.S. If the machine is already running in 64 bit mode the sigp turns into a nop. With this change it doesn't matter in which mode the kernel is started. Reviewd-by: Heiko Carstens <heiko.carstens@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
This commit is contained in:
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@ -52,7 +52,7 @@ __HEAD
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.long 0x02000370,0x60000050 # the channel program the PSW
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.long 0x02000370,0x60000050 # the channel program the PSW
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.long 0x020003c0,0x60000050 # at location 0 is loaded.
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.long 0x020003c0,0x60000050 # at location 0 is loaded.
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.long 0x02000410,0x60000050 # Initial processing starts
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.long 0x02000410,0x60000050 # Initial processing starts
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.long 0x02000460,0x60000050 # at 0xf0 = iplstart.
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.long 0x02000460,0x60000050 # at 0x200 = iplstart.
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.long 0x020004b0,0x60000050
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.long 0x020004b0,0x60000050
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.long 0x02000500,0x60000050
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.long 0x02000500,0x60000050
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.long 0x02000550,0x60000050
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.long 0x02000550,0x60000050
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@ -62,11 +62,54 @@ __HEAD
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.long 0x02000690,0x60000050
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.long 0x02000690,0x60000050
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.long 0x020006e0,0x20000050
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.long 0x020006e0,0x20000050
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.org 0xf0
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.org 0x200
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#
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# subroutine to set architecture mode
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#
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.Lsetmode:
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#ifdef CONFIG_64BIT
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mvi __LC_AR_MODE_ID,1 # set esame flag
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slr %r0,%r0 # set cpuid to zero
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lhi %r1,2 # mode 2 = esame (dump)
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sigp %r1,%r0,0x12 # switch to esame mode
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bras %r13,0f
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.fill 16,4,0x0
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0: lmh %r0,%r15,0(%r13) # clear high-order half of gprs
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sam31 # switch to 31 bit addressing mode
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#else
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mvi __LC_AR_MODE_ID,0 # set ESA flag (mode 0)
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#endif
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br %r14
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#
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# subroutine to wait for end I/O
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#
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.Lirqwait:
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#ifdef CONFIG_64BIT
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mvc 0x1f0(16),.Lnewpsw # set up IO interrupt psw
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lpsw .Lwaitpsw
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.Lioint:
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br %r14
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.align 8
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.Lnewpsw:
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.quad 0x0000000080000000,.Lioint
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#else
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mvc 0x78(8),.Lnewpsw # set up IO interrupt psw
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lpsw .Lwaitpsw
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.Lioint:
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br %r14
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.align 8
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.Lnewpsw:
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.long 0x00080000,0x80000000+.Lioint
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#endif
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.Lwaitpsw:
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.long 0x020a0000,0x80000000+.Lioint
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#
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#
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# subroutine for loading cards from the reader
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# subroutine for loading cards from the reader
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#
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#
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.Lloader:
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.Lloader:
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la %r4,0(%r14)
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la %r3,.Lorb # r2 = address of orb into r2
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la %r3,.Lorb # r2 = address of orb into r2
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la %r5,.Lirb # r4 = address of irb
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la %r5,.Lirb # r4 = address of irb
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la %r6,.Lccws
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la %r6,.Lccws
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@ -83,9 +126,7 @@ __HEAD
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ssch 0(%r3) # load chunk of 1600 bytes
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ssch 0(%r3) # load chunk of 1600 bytes
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bnz .Llderr
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bnz .Llderr
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.Lwait4irq:
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.Lwait4irq:
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mvc 0x78(8),.Lnewpsw # set up IO interrupt psw
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bas %r14,.Lirqwait
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lpsw .Lwaitpsw
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.Lioint:
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c %r1,0xb8 # compare subchannel number
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c %r1,0xb8 # compare subchannel number
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bne .Lwait4irq
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bne .Lwait4irq
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tsch 0(%r5)
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tsch 0(%r5)
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@ -104,7 +145,7 @@ __HEAD
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sr %r0,%r3 # #ccws*80-residual=#bytes read
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sr %r0,%r3 # #ccws*80-residual=#bytes read
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ar %r2,%r0
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ar %r2,%r0
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br %r14 # r2 contains the total size
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br %r4 # r2 contains the total size
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.Lcont:
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.Lcont:
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ahi %r2,0x640 # add 0x640 to total size
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ahi %r2,0x640 # add 0x640 to total size
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@ -128,10 +169,6 @@ __HEAD
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.Lloadp:.long 0,0
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.Lloadp:.long 0,0
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.align 8
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.align 8
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.Lcrash:.long 0x000a0000,0x00000000
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.Lcrash:.long 0x000a0000,0x00000000
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.Lnewpsw:
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.long 0x00080000,0x80000000+.Lioint
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.Lwaitpsw:
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.long 0x020a0000,0x80000000+.Lioint
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.align 8
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.align 8
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.Lccws: .rept 19
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.Lccws: .rept 19
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@ -140,6 +177,7 @@ __HEAD
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.long 0x02200050,0x00000000
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.long 0x02200050,0x00000000
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iplstart:
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iplstart:
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bas %r14,.Lsetmode # Immediately switch to 64 bit mode
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lh %r1,0xb8 # test if subchannel number
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lh %r1,0xb8 # test if subchannel number
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bct %r1,.Lnoload # is valid
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bct %r1,.Lnoload # is valid
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l %r1,0xb8 # load ipl subchannel number
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l %r1,0xb8 # load ipl subchannel number
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@ -209,8 +247,8 @@ iplstart:
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#
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#
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# reset files in VM reader
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# reset files in VM reader
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#
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#
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stidp __LC_SAVE_AREA_SYNC # store cpuid
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stidp .Lcpuid # store cpuid
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tm __LC_SAVE_AREA_SYNC,0xff# running VM ?
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tm .Lcpuid,0xff # running VM ?
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bno .Lnoreset
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bno .Lnoreset
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la %r2,.Lreset
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la %r2,.Lreset
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lhi %r3,26
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lhi %r3,26
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@ -222,23 +260,14 @@ iplstart:
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tm 31(%r5),0xff # bits is set in the schib
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tm 31(%r5),0xff # bits is set in the schib
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bz .Lnoreset
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bz .Lnoreset
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.Lwaitforirq:
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.Lwaitforirq:
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mvc 0x78(8),.Lrdrnewpsw # set up IO interrupt psw
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bas %r14,.Lirqwait # wait for IO interrupt
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.Lwaitrdrirq:
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lpsw .Lrdrwaitpsw
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.Lrdrint:
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c %r1,0xb8 # compare subchannel number
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c %r1,0xb8 # compare subchannel number
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bne .Lwaitrdrirq
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bne .Lwaitforirq
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la %r5,.Lirb
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la %r5,.Lirb
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tsch 0(%r5)
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tsch 0(%r5)
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.Lnoreset:
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.Lnoreset:
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b .Lnoload
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b .Lnoload
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.align 8
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.Lrdrnewpsw:
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.long 0x00080000,0x80000000+.Lrdrint
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.Lrdrwaitpsw:
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.long 0x020a0000,0x80000000+.Lrdrint
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#
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#
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# everything loaded, go for it
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# everything loaded, go for it
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#
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#
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@ -254,6 +283,8 @@ iplstart:
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.byte 0xc8,0xd6,0xd3,0xc4 # "change rdr all keep nohold"
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.byte 0xc8,0xd6,0xd3,0xc4 # "change rdr all keep nohold"
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.L_eof: .long 0xc5d6c600 /* C'EOF' */
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.L_eof: .long 0xc5d6c600 /* C'EOF' */
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.L_hdr: .long 0xc8c4d900 /* C'HDR' */
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.L_hdr: .long 0xc8c4d900 /* C'HDR' */
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.align 8
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.Lcpuid:.fill 8,1,0
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#
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#
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# SALIPL loader support. Based on a patch by Rob van der Heij.
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# SALIPL loader support. Based on a patch by Rob van der Heij.
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@ -263,6 +294,7 @@ iplstart:
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.org 0x800
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.org 0x800
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ENTRY(start)
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ENTRY(start)
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stm %r0,%r15,0x07b0 # store registers
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stm %r0,%r15,0x07b0 # store registers
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bas %r14,.Lsetmode # Immediately switch to 64 bit mode
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basr %r12,%r0
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basr %r12,%r0
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.base:
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.base:
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l %r11,.parm
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l %r11,.parm
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@ -343,6 +375,18 @@ ENTRY(startup)
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ENTRY(startup_kdump)
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ENTRY(startup_kdump)
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j .Lep_startup_kdump
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j .Lep_startup_kdump
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.Lep_startup_normal:
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.Lep_startup_normal:
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#ifdef CONFIG_64BIT
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mvi __LC_AR_MODE_ID,1 # set esame flag
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slr %r0,%r0 # set cpuid to zero
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lhi %r1,2 # mode 2 = esame (dump)
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sigp %r1,%r0,0x12 # switch to esame mode
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bras %r13,0f
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.fill 16,4,0x0
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0: lmh %r0,%r15,0(%r13) # clear high-order half of gprs
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sam31 # switch to 31 bit addressing mode
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#else
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mvi __LC_AR_MODE_ID,0 # set ESA flag (mode 0)
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#endif
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basr %r13,0 # get base
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basr %r13,0 # get base
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.LPG0:
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.LPG0:
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xc 0x200(256),0x200 # partially clear lowcore
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xc 0x200(256),0x200 # partially clear lowcore
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@ -410,22 +454,17 @@ ENTRY(startup_kdump)
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#endif
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#endif
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#ifdef CONFIG_64BIT
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#ifdef CONFIG_64BIT
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mvi __LC_AR_MODE_ID,1 # set esame flag
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/* Continue with 64bit startup code in head64.S */
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slr %r0,%r0 # set cpuid to zero
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lhi %r1,2 # mode 2 = esame (dump)
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sigp %r1,%r0,0x12 # switch to esame mode
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sam64 # switch to 64 bit mode
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sam64 # switch to 64 bit mode
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larl %r13,4f
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lmh %r0,%r15,0(%r13) # clear high-order half
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jg startup_continue
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jg startup_continue
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4: .fill 16,4,0x0
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#else
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#else
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mvi __LC_AR_MODE_ID,0 # set ESA flag (mode 0)
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/* Continue with 31bit startup code in head31.S */
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l %r13,4f-.LPG0(%r13)
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l %r13,4f-.LPG0(%r13)
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b 0(%r13)
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b 0(%r13)
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.align 8
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.align 8
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4: .long startup_continue
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4: .long startup_continue
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#endif
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#endif
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.align 8
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.align 8
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5: .long 0x7fffffff,0xffffffff
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5: .long 0x7fffffff,0xffffffff
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