Merge branches 'fixes' and 'misc' into for-next
This commit is contained in:
commit
53f1d9afb4
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@ -23,6 +23,7 @@
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#include <asm/ptrace.h>
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#include <asm/domain.h>
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#include <asm/opcodes-virt.h>
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#include <asm/asm-offsets.h>
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#define IOMEM(x) (x)
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@ -174,6 +175,47 @@
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restore_irqs_notrace \oldcpsr
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.endm
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/*
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* Get current thread_info.
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*/
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.macro get_thread_info, rd
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ARM( mov \rd, sp, lsr #13 )
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THUMB( mov \rd, sp )
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THUMB( lsr \rd, \rd, #13 )
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mov \rd, \rd, lsl #13
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.endm
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/*
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* Increment/decrement the preempt count.
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*/
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#ifdef CONFIG_PREEMPT_COUNT
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.macro inc_preempt_count, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
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add \tmp, \tmp, #1 @ increment it
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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.macro dec_preempt_count, ti, tmp
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ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
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sub \tmp, \tmp, #1 @ decrement it
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str \tmp, [\ti, #TI_PREEMPT]
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.endm
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.macro dec_preempt_count_ti, ti, tmp
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get_thread_info \ti
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dec_preempt_count \ti, \tmp
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.endm
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#else
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.macro inc_preempt_count, ti, tmp
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.endm
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.macro dec_preempt_count, ti, tmp
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.endm
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.macro dec_preempt_count_ti, ti, tmp
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.endm
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#endif
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#define USER(x...) \
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9999: x; \
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.pushsection __ex_table,"a"; \
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@ -221,4 +221,23 @@ static inline int cpu_is_xsc3(void)
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#define cpu_is_xscale() 1
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#endif
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/*
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* Marvell's PJ4 core is based on V7 version. It has some modification
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* for coprocessor setting. For this reason, we need a way to distinguish
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* it.
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*/
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#ifndef CONFIG_CPU_PJ4
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#define cpu_is_pj4() 0
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#else
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static inline int cpu_is_pj4(void)
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{
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unsigned int id;
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id = read_cpuid_id();
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if ((id & 0xfffffff0) == 0x562f5840)
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return 1;
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return 0;
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}
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#endif
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#endif
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@ -39,7 +39,7 @@ ssize_t copy_oldmem_page(unsigned long pfn, char *buf,
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if (!csize)
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return 0;
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vaddr = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
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vaddr = ioremap(__pfn_to_phys(pfn), PAGE_SIZE);
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if (!vaddr)
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return -ENOMEM;
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@ -236,11 +236,6 @@
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movs pc, lr @ return & move spsr_svc into cpsr
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.endm
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.macro get_thread_info, rd
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mov \rd, sp, lsr #13
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mov \rd, \rd, lsl #13
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.endm
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@
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@ 32-bit wide "mov pc, reg"
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@
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@ -306,12 +301,6 @@
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.endm
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#endif /* ifdef CONFIG_CPU_V7M / else */
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.macro get_thread_info, rd
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mov \rd, sp
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lsr \rd, \rd, #13
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mov \rd, \rd, lsl #13
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.endm
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@
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@ 32-bit wide "mov pc, reg"
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@
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@ -17,6 +17,7 @@
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/thread_notify.h>
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#include <asm/cputype.h>
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static int iwmmxt_do(struct notifier_block *self, unsigned long cmd, void *t)
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{
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@ -80,6 +81,9 @@ static int __init pj4_cp0_init(void)
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{
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u32 cp_access;
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if (!cpu_is_pj4())
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return 0;
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cp_access = pj4_cp_access_read() & ~0xf;
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pj4_cp_access_write(cp_access);
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@ -39,6 +39,7 @@
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#include <asm/processor.h>
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#include <asm/thread_notify.h>
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#include <asm/stacktrace.h>
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#include <asm/system_misc.h>
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#include <asm/mach/time.h>
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#include <asm/tls.h>
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@ -100,7 +101,7 @@ void soft_restart(unsigned long addr)
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u64 *stack = soft_restart_stack + ARRAY_SIZE(soft_restart_stack);
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/* Disable interrupts first */
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local_irq_disable();
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raw_local_irq_disable();
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local_fiq_disable();
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/* Disable the L2 if we're the last man standing. */
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@ -445,6 +445,7 @@ die_sig:
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if (user_debug & UDBG_UNDEFINED) {
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printk(KERN_INFO "%s (%d): undefined instruction: pc=%p\n",
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current->comm, task_pid_nr(current), pc);
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__show_regs(regs);
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dump_instr(KERN_INFO, regs);
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}
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#endif
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@ -137,11 +137,16 @@ static void dcscb_power_down(void)
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v7_exit_coherency_flush(all);
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/*
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* This is a harmless no-op. On platforms with a real
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* outer cache this might either be needed or not,
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* depending on where the outer cache sits.
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* A full outer cache flush could be needed at this point
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* on platforms with such a cache, depending on where the
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* outer cache sits. In some cases the notion of a "last
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* cluster standing" would need to be implemented if the
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* outer cache is shared across clusters. In any case, when
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* the outer cache needs flushing, there is no concurrent
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* access to the cache controller to worry about and no
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* special locking besides what is already provided by the
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* MCPM state machinery is needed.
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*/
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outer_flush_all();
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/*
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* Disable cluster-level coherency by masking
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@ -120,25 +120,7 @@ static const struct prot_bits pte_bits[] = {
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};
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static const struct prot_bits section_bits[] = {
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#ifndef CONFIG_ARM_LPAE
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/* These are approximate */
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{
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.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = 0,
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.set = " ro",
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}, {
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.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_AP_WRITE,
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.set = " RW",
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}, {
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.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_AP_READ,
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.set = "USR ro",
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}, {
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.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.set = "USR RW",
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#else
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#ifdef CONFIG_ARM_LPAE
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{
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.mask = PMD_SECT_USER,
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.val = PMD_SECT_USER,
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.val = PMD_SECT_RDONLY,
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.set = "ro",
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.clear = "RW",
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#elif __LINUX_ARM_ARCH__ >= 6
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{
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.mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_APX | PMD_SECT_AP_WRITE,
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.set = " ro",
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}, {
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.mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_AP_WRITE,
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.set = " RW",
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}, {
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.mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_AP_READ,
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.set = "USR ro",
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}, {
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.mask = PMD_SECT_APX | PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.set = "USR RW",
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#else /* ARMv4/ARMv5 */
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/* These are approximate */
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{
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.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = 0,
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.set = " ro",
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}, {
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.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_AP_WRITE,
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.set = " RW",
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}, {
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.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_AP_READ,
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.set = "USR ro",
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}, {
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.mask = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.val = PMD_SECT_AP_READ | PMD_SECT_AP_WRITE,
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.set = "USR RW",
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#endif
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}, {
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.mask = PMD_SECT_XN,
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@ -8,9 +8,12 @@
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/vfpmacros.h>
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#include "../kernel/entry-header.S"
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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@ VFP entry point.
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@
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@ IRQs disabled.
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@
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ENTRY(do_vfp)
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#ifdef CONFIG_PREEMPT_COUNT
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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add r11, r4, #1 @ increment it
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str r11, [r10, #TI_PREEMPT]
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#endif
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inc_preempt_count r10, r4
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enable_irq
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ldr r4, .LCvfp
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ldr r11, [r10, #TI_CPU] @ CPU number
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@ -35,12 +34,7 @@ ENTRY(do_vfp)
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ENDPROC(do_vfp)
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ENTRY(vfp_null_entry)
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#ifdef CONFIG_PREEMPT_COUNT
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get_thread_info r10
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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sub r11, r4, #1 @ decrement it
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str r11, [r10, #TI_PREEMPT]
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#endif
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dec_preempt_count_ti r10, r4
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mov pc, lr
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ENDPROC(vfp_null_entry)
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@ -53,12 +47,7 @@ ENDPROC(vfp_null_entry)
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__INIT
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ENTRY(vfp_testing_entry)
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#ifdef CONFIG_PREEMPT_COUNT
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get_thread_info r10
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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sub r11, r4, #1 @ decrement it
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str r11, [r10, #TI_PREEMPT]
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#endif
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dec_preempt_count_ti r10, r4
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ldr r0, VFP_arch_address
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str r0, [r0] @ set to non-zero value
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mov pc, r9 @ we have handled the fault
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@ -14,10 +14,13 @@
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* r10 points at the start of the private FP workspace in the thread structure
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* sp points to a struct pt_regs (as defined in include/asm/proc/ptrace.h)
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/thread_info.h>
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#include <asm/vfpmacros.h>
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#include <linux/kern_levels.h>
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#include "../kernel/entry-header.S"
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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.macro DBGSTR, str
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#ifdef DEBUG
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@ -179,12 +182,7 @@ vfp_hw_state_valid:
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@ else it's one 32-bit instruction, so
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@ always subtract 4 from the following
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@ instruction address.
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#ifdef CONFIG_PREEMPT_COUNT
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get_thread_info r10
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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sub r11, r4, #1 @ decrement it
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str r11, [r10, #TI_PREEMPT]
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#endif
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dec_preempt_count_ti r10, r4
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mov pc, r9 @ we think we have handled things
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@ -203,12 +201,7 @@ look_for_VFP_exceptions:
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@ not recognised by VFP
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DBGSTR "not VFP"
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#ifdef CONFIG_PREEMPT_COUNT
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get_thread_info r10
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ldr r4, [r10, #TI_PREEMPT] @ get preempt count
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sub r11, r4, #1 @ decrement it
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str r11, [r10, #TI_PREEMPT]
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#endif
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dec_preempt_count_ti r10, r4
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mov pc, lr
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process_exception:
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