scsi: ufs-qcom: add number of lanes per direction
Different platform may have different number of lanes for the UFS link. Add parameter to device tree specifying how many lanes should be configured for the UFS link. Reviewed-by: Hannes Reinecke <hare@suse.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Gilad Broner <gbroner@codeaurora.org> Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -38,6 +38,9 @@ Optional properties:
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defined or a value in the array is "0" then it is assumed
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that the frequency is set by the parent clock or a
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fixed rate clock source.
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-lanes-per-direction : number of lanes available per direction - either 1 or 2.
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Note that it is assume same number of lanes is used both
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directions at once. If not specified, default is 2 lanes per direction.
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Note: If above properties are not defined it can be assumed that the supply
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regulators or clocks are always on.
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2013-2015, Linux Foundation. All rights reserved.
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* Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@ -132,21 +132,24 @@ static int ufs_qcom_enable_lane_clks(struct ufs_qcom_host *host)
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if (err)
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goto disable_rx_l0;
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err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
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host->rx_l1_sync_clk);
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if (err)
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goto disable_tx_l0;
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if (host->hba->lanes_per_direction > 1) {
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err = ufs_qcom_host_clk_enable(dev, "rx_lane1_sync_clk",
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host->rx_l1_sync_clk);
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if (err)
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goto disable_tx_l0;
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err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
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host->tx_l1_sync_clk);
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if (err)
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goto disable_rx_l1;
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err = ufs_qcom_host_clk_enable(dev, "tx_lane1_sync_clk",
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host->tx_l1_sync_clk);
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if (err)
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goto disable_rx_l1;
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}
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host->is_lane_clks_enabled = true;
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goto out;
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disable_rx_l1:
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clk_disable_unprepare(host->rx_l1_sync_clk);
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if (host->hba->lanes_per_direction > 1)
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clk_disable_unprepare(host->rx_l1_sync_clk);
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disable_tx_l0:
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clk_disable_unprepare(host->tx_l0_sync_clk);
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disable_rx_l0:
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@ -170,14 +173,16 @@ static int ufs_qcom_init_lane_clks(struct ufs_qcom_host *host)
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if (err)
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goto out;
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err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
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&host->rx_l1_sync_clk);
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if (err)
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goto out;
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err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
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&host->tx_l1_sync_clk);
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/* In case of single lane per direction, don't read lane1 clocks */
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if (host->hba->lanes_per_direction > 1) {
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err = ufs_qcom_host_clk_get(dev, "rx_lane1_sync_clk",
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&host->rx_l1_sync_clk);
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if (err)
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goto out;
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err = ufs_qcom_host_clk_get(dev, "tx_lane1_sync_clk",
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&host->tx_l1_sync_clk);
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}
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out:
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return err;
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}
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@ -40,6 +40,8 @@
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#include "ufshcd.h"
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#include "ufshcd-pltfrm.h"
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#define UFSHCD_DEFAULT_LANES_PER_DIRECTION 2
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static int ufshcd_parse_clock_info(struct ufs_hba *hba)
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{
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int ret = 0;
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@ -277,6 +279,21 @@ void ufshcd_pltfrm_shutdown(struct platform_device *pdev)
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}
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EXPORT_SYMBOL_GPL(ufshcd_pltfrm_shutdown);
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static void ufshcd_init_lanes_per_dir(struct ufs_hba *hba)
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{
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struct device *dev = hba->dev;
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int ret;
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ret = of_property_read_u32(dev->of_node, "lanes-per-direction",
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&hba->lanes_per_direction);
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if (ret) {
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dev_dbg(hba->dev,
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"%s: failed to read lanes-per-direction, ret=%d\n",
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__func__, ret);
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hba->lanes_per_direction = UFSHCD_DEFAULT_LANES_PER_DIRECTION;
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}
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}
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/**
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* ufshcd_pltfrm_init - probe routine of the driver
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* @pdev: pointer to Platform device handle
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@ -331,6 +348,8 @@ int ufshcd_pltfrm_init(struct platform_device *pdev,
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pm_runtime_set_active(&pdev->dev);
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pm_runtime_enable(&pdev->dev);
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ufshcd_init_lanes_per_dir(hba);
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err = ufshcd_init(hba, mmio_base, irq);
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if (err) {
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dev_err(dev, "Initialization failed\n");
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@ -40,6 +40,7 @@
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#include <linux/async.h>
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#include <linux/devfreq.h>
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#include <linux/of.h>
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#include "ufshcd.h"
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#include "unipro.h"
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@ -509,6 +509,8 @@ struct ufs_hba {
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bool wlun_dev_clr_ua;
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/* Number of lanes available (1 or 2) for Rx/Tx */
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u32 lanes_per_direction;
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struct ufs_pa_layer_attr pwr_info;
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struct ufs_pwr_mode_info max_pwr_info;
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