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Renesas ARM Based SoC DT Updates for v5.1 

* R-Car H2 (r8a7790) based Stout board
   - Convert to new LVDS DT bindings
 
 * R-Car H1 (r8a7779) and M1A (r8a7778) SoCs
   - Describe HSCIF0/1 devices in DT
 
 * RZ/G1M (r8a7743) SoC
   - Correct sort order of the RWDT node
   - Remove aliases: should be defined in board rather than SoC DT if needed
   - Remove generic compatible string from iic3: it is not compatible
 
 * RZ/G1N (r8a7744) SoC
   - Describe LVDS and DU devices in DT
   - Correct sort order of VSP and MSIOF noces
 
 * RZ/G1C (r8a7747) based iWave SBC
   - Enable RTC
 
 * RZ/A2M (r7s9210) SoC and EVB
   - Initial support
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Merge tag 'renesas-arm-dt-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt

Renesas ARM Based SoC DT Updates for v5.1

* R-Car H2 (r8a7790) based Stout board
  - Convert to new LVDS DT bindings

* R-Car H1 (r8a7779) and M1A (r8a7778) SoCs
  - Describe HSCIF0/1 devices in DT

* RZ/G1M (r8a7743) SoC
  - Correct sort order of the RWDT node
  - Remove aliases: should be defined in board rather than SoC DT if needed
  - Remove generic compatible string from iic3: it is not compatible

* RZ/G1N (r8a7744) SoC
  - Describe LVDS and DU devices in DT
  - Correct sort order of VSP and MSIOF noces

* RZ/G1C (r8a7747) based iWave SBC
  - Enable RTC

* RZ/A2M (r7s9210) SoC and EVB
  - Initial support

* tag 'renesas-arm-dt-for-v5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: dts: r8a7744: Add LVDS support
  ARM: dts: r8a7744: Add DU support
  ARM: dts: r7s9210-rza2mevb: Add support for RZ/A2M EVB
  ARM: dts: r7s9210: Initial SoC device tree
  ARM: dts: r8a7779: Add HSCIF0/1 device nodes
  ARM: dts: r8a7778: Add HSCIF0/1 support
  ARM: dts: r8a7743: Fix sorting of rwdt node
  ARM: dts: r8a7743: Remove aliases from SoC dtsi
  ARM: dts: r8a7743: Remove generic compatible string from iic3
  ARM: dts: r8a7744: Fix sorting of vsp and msiof nodes
  ARM: dts: iwg23s-sbc: Enable RTC
  ARM: dts: stout: Convert to new LVDS DT bindings

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2019-02-15 15:45:54 +01:00
parent ec38fad35f 1feef0ac19
commit 550a43b310
10 changed files with 508 additions and 113 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@ -847,6 +847,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r7s72100-genmai.dtb \
r7s72100-gr-peach.dtb \
r7s72100-rskrza1.dtb \
r7s9210-rza2mevb.dtb \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-iwg20d-q7.dtb \

82
arch/arm/boot/dts/r7s9210-rza2mevb.dts Normal file
View File

@ -0,0 +1,82 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the RZA2MEVB board
*
* Copyright (C) 2018 Renesas Electronics
*
*/
/dts-v1/;
#include "r7s9210.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s9210-pinctrl.h>
/ {
model = "RZA2MEVB";
compatible = "renesas,rza2mevb", "renesas,r7s9210";
aliases {
serial0 = &scif4;
};
chosen {
bootargs = "ignore_loglevel";
stdout-path = "serial0:115200n8";
};
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x00800000>; /* HyperRAM */
};
lbsc {
#address-cells = <1>;
#size-cells = <1>;
};
leds {
compatible = "gpio-leds";
red {
gpios = <&pinctrl RZA2_PIN(PORT6, 0) GPIO_ACTIVE_HIGH>;
};
green {
gpios = <&pinctrl RZA2_PIN(PORTC, 1) GPIO_ACTIVE_HIGH>;
};
};
};
/* EXTAL */
&extal_clk {
clock-frequency = <24000000>; /* 24MHz */
};
/* RTC_X1 */
&rtc_x1_clk {
clock-frequency = <32768>;
};
&pinctrl {
/* Serial Console */
scif4_pins: serial4 {
pinmux = <RZA2_PINMUX(PORT9, 0, 4)>, /* TxD4 */
<RZA2_PINMUX(PORT9, 1, 4)>; /* RxD4 */
};
};
/* High resolution System tick timers */
&ostm0 {
status = "okay";
};
&ostm1 {
status = "okay";
};
/* Serial Console */
&scif4 {
pinctrl-names = "default";
pinctrl-0 = <&scif4_pins>;
status = "okay";
};

218
arch/arm/boot/dts/r7s9210.dtsi Normal file
View File

@ -0,0 +1,218 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the R7S9210 SoC
*
* Copyright (C) 2018 Renesas Electronics Corporation
*
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/r7s9210-cpg-mssr.h>
/ {
compatible = "renesas,r7s9210";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
/* External clocks */
extal_clk: extal {
#clock-cells = <0>;
compatible = "fixed-clock";
/* Value must be set by board */
clock-frequency = <0>;
};
rtc_x1_clk: rtc_x1 {
#clock-cells = <0>;
compatible = "fixed-clock";
/* If clk present, value (32678) must be set by board */
clock-frequency = <0>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
clock-frequency = <528000000>;
next-level-cache = <&L2>;
};
};
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
L2: cache-controller@1f003000 {
compatible = "arm,pl310-cache";
reg = <0x1f003000 0x1000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
arm,early-bresp-disable;
arm,full-line-zero-disable;
cache-unified;
cache-level = <2>;
};
scif0: serial@e8007000 {
compatible = "renesas,scif-r7s9210";
reg = <0xe8007000 0x18>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD 47>;
clock-names = "fck";
power-domains = <&cpg>;
status = "disabled";
};
scif1: serial@e8007800 {
compatible = "renesas,scif-r7s9210";
reg = <0xe8007800 0x18>;
interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD 46>;
clock-names = "fck";
power-domains = <&cpg>;
status = "disabled";
};
scif2: serial@e8008000 {
compatible = "renesas,scif-r7s9210";
reg = <0xe8008000 0x18>;
interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD 45>;
clock-names = "fck";
power-domains = <&cpg>;
status = "disabled";
};
scif3: serial@e8008800 {
compatible = "renesas,scif-r7s9210";
reg = <0xe8008800 0x18>;
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD 44>;
clock-names = "fck";
power-domains = <&cpg>;
status = "disabled";
};
scif4: serial@e8009000 {
compatible = "renesas,scif-r7s9210";
reg = <0xe8009000 0x18>;
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi",
"bri", "dri", "tei";
clocks = <&cpg CPG_MOD 43>;
clock-names = "fck";
power-domains = <&cpg>;
status = "disabled";
};
ostm0: timer@e803b000 {
compatible = "renesas,r7s9210-ostm", "renesas,ostm";
reg = <0xe803b000 0x30>;
interrupts = <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD 36>;
clock-names = "ostm0";
power-domains = <&cpg>;
status = "disabled";
};
ostm1: timer@e803c000 {
compatible = "renesas,r7s9210-ostm", "renesas,ostm";
reg = <0xe803c000 0x30>;
interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD 35>;
clock-names = "ostm1";
power-domains = <&cpg>;
status = "disabled";
};
ostm2: timer@e803d000 {
compatible = "renesas,r7s9210-ostm", "renesas,ostm";
reg = <0xe803d000 0x30>;
interrupts = <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>;
clocks = <&cpg CPG_MOD 34>;
clock-names = "ostm2";
power-domains = <&cpg>;
status = "disabled";
};
gic: interrupt-controller@e8221000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
reg = <0xe8221000 0x1000>,
<0xe8222000 0x1000>;
};
cpg: clock-controller@fcfe0010 {
compatible = "renesas,r7s9210-cpg-mssr";
reg = <0xfcfe0010 0x455>;
clocks = <&extal_clk>;
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
};
wdt: watchdog@fcfe7000 {
compatible = "renesas,r7s9210-wdt", "renesas,rza-wdt";
reg = <0xfcfe7000 0x26>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_CORE R7S9210_CLK_P0>;
};
bsid: chipid@fcfe8004 {
compatible = "renesas,bsid";
reg = <0xfcfe8004 4>;
};
pinctrl: pin-controller@fcffe000 {
compatible = "renesas,r7s9210-pinctrl";
reg = <0xfcffe000 0x1000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 176>;
};
};
};

43
arch/arm/boot/dts/r8a7743.dtsi
View File

@ -15,25 +15,6 @@
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &iic0;
i2c7 = &iic1;
i2c8 = &iic3;
spi0 = &qspi;
spi1 = &msiof0;
spi2 = &msiof1;
spi3 = &msiof2;
vin0 = &vin0;
vin1 = &vin1;
vin2 = &vin2;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
@ -154,6 +135,16 @@
#size-cells = <2>;
ranges;
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7743-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7743",
"renesas,rcar-gen2-gpio";
@ -310,16 +301,6 @@
reg = <0 0xe6160000 0 0x100>;
};
rwdt: watchdog@e6020000 {
compatible = "renesas,r8a7743-wdt",
"renesas,rcar-gen2-wdt";
reg = <0 0xe6020000 0 0x0c>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 402>;
status = "disabled";
};
sysc: system-controller@e6180000 {
compatible = "renesas,r8a7743-sysc";
reg = <0 0xe6180000 0 0x200>;
@ -564,9 +545,7 @@
/* doesn't need pinmux */
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7743",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
compatible = "renesas,iic-r8a7743";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;

188
arch/arm/boot/dts/r8a7744.dtsi
View File

@ -998,6 +998,54 @@
status = "disabled";
};
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7744",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 000>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
<&dmac1 0x51>, <&dmac1 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 000>;
status = "disabled";
};
msiof1: spi@e6e10000 {
compatible = "renesas,msiof-r8a7744",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e10000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
<&dmac1 0x55>, <&dmac1 0x56>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 208>;
status = "disabled";
};
msiof2: spi@e6e00000 {
compatible = "renesas,msiof-r8a7744",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 205>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>,
<&dmac1 0x41>, <&dmac1 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 205>;
status = "disabled";
};
pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a7744", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>;
@ -1068,54 +1116,6 @@
status = "disabled";
};
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7744",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 000>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
<&dmac1 0x51>, <&dmac1 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 000>;
status = "disabled";
};
msiof1: spi@e6e10000 {
compatible = "renesas,msiof-r8a7744",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e10000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
<&dmac1 0x55>, <&dmac1 0x56>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 208>;
status = "disabled";
};
msiof2: spi@e6e00000 {
compatible = "renesas,msiof-r8a7744",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 205>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>,
<&dmac1 0x41>, <&dmac1 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 205>;
status = "disabled";
};
can0: can@e6e80000 {
compatible = "renesas,can-r8a7744",
"renesas,rcar-gen2-can";
@ -1589,33 +1589,6 @@
resets = <&cpg 408>;
};
vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 131>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 131>;
};
vsp@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 128>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 128>;
};
vsp@fe938000 {
compatible = "renesas,vsp1";
reg = <0 0xfe938000 0 0x8000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 127>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 127>;
};
pciec: pcie@fe000000 {
compatible = "renesas,pcie-r8a7744",
"renesas,pcie-rcar-gen2";
@ -1644,9 +1617,42 @@
status = "disabled";
};
vsp@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 131>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 131>;
};
vsp@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 128>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 128>;
};
vsp@fe938000 {
compatible = "renesas,vsp1";
reg = <0 0xfe938000 0 0x8000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 127>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 127>;
};
du: display@feb00000 {
reg = <0 0xfeb00000 0 0x40000>,
<0 0xfeb90000 0 0x1c>;
compatible = "renesas,du-r8a7744";
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
status = "disabled";
ports {
#address-cells = <1>;
@ -1660,10 +1666,36 @@
port@1 {
reg = <1>;
du_out_lvds0: endpoint {
remote-endpoint = <&lvds0_in>;
};
};
};
};
lvds0: lvds@feb90000 {
compatible = "renesas,r8a7744-lvds";
reg = <0 0xfeb90000 0 0x1c>;
clocks = <&cpg CPG_MOD 726>;
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
resets = <&cpg 726>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds0_in: endpoint {
remote-endpoint = <&du_out_lvds0>;
};
};
port@1 {
reg = <1>;
lvds0_out: endpoint {
};
};
};
/* placeholder */
};
prr: chipid@ff000044 {

18
arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
View File

@ -84,12 +84,30 @@
clock-frequency = <20000000>;
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
rtc@51 {
compatible = "nxp,pcf85263";
reg = <0x51>;
};
};
&pfc {
avb_pins: avb {
groups = "avb_mdio", "avb_gmii_tx_rx";
function = "avb";
};
i2c3_pins: i2c3 {
groups = "i2c3_c";
function = "i2c3";
};
mmc_pins_uhs: mmc_uhs {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";

28
arch/arm/boot/dts/r8a7778.dtsi
View File

@ -367,6 +367,30 @@
status = "disabled";
};
hscif0: serial@ffe48000 {
compatible = "renesas,hscif-r8a7778",
"renesas,rcar-gen1-hscif", "renesas,hscif";
reg = <0xffe48000 96>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSCIF0>,
<&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
status = "disabled";
};
hscif1: serial@ffe49000 {
compatible = "renesas,hscif-r8a7778",
"renesas,rcar-gen1-hscif", "renesas,hscif";
reg = <0xffe49000 96>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7778_CLK_HSCIF1>,
<&cpg_clocks R8A7778_CLK_S>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
status = "disabled";
};
mmcif: mmc@ffe4e000 {
compatible = "renesas,mmcif-r8a7778", "renesas,sh-mmcif";
reg = <0xffe4e000 0x100>;
@ -535,6 +559,8 @@
<&cpg_clocks R8A7778_CLK_P>,
<&cpg_clocks R8A7778_CLK_P>,
<&cpg_clocks R8A7778_CLK_P>,
<&cpg_clocks R8A7778_CLK_S>,
<&cpg_clocks R8A7778_CLK_S>,
<&cpg_clocks R8A7778_CLK_P>,
<&cpg_clocks R8A7778_CLK_P>,
<&cpg_clocks R8A7778_CLK_P>,
@ -551,6 +577,7 @@
R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
R8A7778_CLK_HSCIF0 R8A7778_CLK_HSCIF1
R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
@ -560,6 +587,7 @@
clock-output-names =
"i2c0", "i2c1", "i2c2", "i2c3", "scif0",
"scif1", "scif2", "scif3", "scif4", "scif5",
"hscif0", "hscif1",
"tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
"ssi2", "ssi3", "sru", "hspi";
};

26
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -287,6 +287,32 @@
status = "disabled";
};
hscif0: serial@ffe48000 {
compatible = "renesas,hscif-r8a7779",
"renesas,rcar-gen1-hscif", "renesas,hscif";
reg = <0xffe48000 96>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_HSCIF0>,
<&cpg_clocks R8A7779_CLK_S>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
status = "disabled";
};
hscif1: serial@ffe49000 {
compatible = "renesas,hscif-r8a7779",
"renesas,rcar-gen1-hscif", "renesas,hscif";
reg = <0xffe49000 96>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7779_CLK_HSCIF1>,
<&cpg_clocks R8A7779_CLK_S>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
power-domains = <&cpg_clocks>;
status = "disabled";
};
pfc: pin-controller@fffc0000 {
compatible = "renesas,pfc-r8a7779";
reg = <0xfffc0000 0x23c>;

15
arch/arm/boot/dts/r8a7790-stout.dts
View File

@ -94,9 +94,8 @@
status = "okay";
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
<&osc1_clk>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0";
clock-names = "du.0", "du.1", "du.2", "dclkin.0";
ports {
port@0 {
@ -104,11 +103,21 @@
remote-endpoint = <&adv7511_in>;
};
};
};
};
&lvds0 {
ports {
port@1 {
lvds_connector0: endpoint {
};
};
port@2 {
};
};
&lvds1 {
ports {
port@1 {
lvds_connector1: endpoint {
};
};

2
include/dt-bindings/clock/r8a7778-clock.h
View File

@ -30,6 +30,8 @@
#define R8A7778_CLK_SCIF3 23
#define R8A7778_CLK_SCIF4 22
#define R8A7778_CLK_SCIF5 21
#define R8A7778_CLK_HSCIF0 19
#define R8A7778_CLK_HSCIF1 18
#define R8A7778_CLK_TMU0 16
#define R8A7778_CLK_TMU1 15
#define R8A7778_CLK_TMU2 14