davinci: update pin-multiplexing support
Update MUX support to be more general and useful across multiple SoCs in the DaVinci family. Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
This commit is contained in:
Kevin Hilman
parent
617b925f94
commit
5526b3f7e3
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@ -18,6 +18,32 @@ config MACH_DAVINCI_EVM
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Configure this option to specify the whether the board used
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for development is a DaVinci EVM
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config DAVINCI_MUX
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bool "DAVINCI multiplexing support"
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depends on ARCH_DAVINCI
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default y
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help
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Pin multiplexing support for DAVINCI boards. If your bootloader
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sets the multiplexing correctly, say N. Otherwise, or if unsure,
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say Y.
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config DAVINCI_MUX_DEBUG
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bool "Multiplexing debug output"
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depends on DAVINCI_MUX
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help
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Makes the multiplexing functions print out a lot of debug info.
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This is useful if you want to find out the correct values of the
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multiplexing registers.
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config DAVINCI_MUX_WARNINGS
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bool "Warn about pins the bootloader didn't set up"
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depends on DAVINCI_MUX
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help
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Choose Y here to warn whenever driver initialization logic needs
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to change the pin multiplexing setup. When there are no warnings
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printed, it's safe to deselect DAVINCI_MUX for your product.
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config DAVINCI_RESET_CLOCKS
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bool "Reset unused clocks during boot"
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depends on ARCH_DAVINCI
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@ -5,7 +5,9 @@
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# Common objects
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obj-y := time.o irq.o clock.o serial.o io.o id.o psc.o \
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gpio.o mux.o devices.o dma.o usb.o
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gpio.o devices.o dma.o usb.o
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obj-$(CONFIG_DAVINCI_MUX) += mux.o
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# Board specific
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obj-$(CONFIG_MACH_DAVINCI_EVM) += board-evm.o
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@ -21,6 +21,8 @@
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#include <mach/hardware.h>
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#include <mach/i2c.h>
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#include <mach/irqs.h>
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#include <mach/cputype.h>
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#include <mach/mux.h>
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#define DAVINCI_I2C_BASE 0x01C21000
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@ -45,6 +47,9 @@ static struct platform_device davinci_i2c_device = {
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void __init davinci_init_i2c(struct davinci_i2c_platform_data *pdata)
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{
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if (cpu_is_davinci_dm644x())
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davinci_cfg_reg(DM644X_I2C);
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davinci_i2c_device.dev.platform_data = pdata;
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(void) platform_device_register(&davinci_i2c_device);
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}
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@ -1,55 +1,183 @@
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/*
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* DaVinci pin multiplexing defines
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* Table of the DAVINCI register configurations for the PINMUX combinations
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*
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* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
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*
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* Based on linux/include/asm-arm/arch-omap/mux.h:
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* Copyright (C) 2003 - 2005 Nokia Corporation
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*
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* Written by Tony Lindgren
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Copyright (C) 2008 Texas Instruments.
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*/
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#ifndef __ASM_ARCH_MUX_H
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#define __ASM_ARCH_MUX_H
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#define DAVINCI_MUX_AEAW0 0
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#define DAVINCI_MUX_AEAW1 1
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#define DAVINCI_MUX_AEAW2 2
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#define DAVINCI_MUX_AEAW3 3
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#define DAVINCI_MUX_AEAW4 4
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#define DAVINCI_MUX_AECS4 10
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#define DAVINCI_MUX_AECS5 11
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#define DAVINCI_MUX_VLYNQWD0 12
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#define DAVINCI_MUX_VLYNQWD1 13
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#define DAVINCI_MUX_VLSCREN 14
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#define DAVINCI_MUX_VLYNQEN 15
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#define DAVINCI_MUX_HDIREN 16
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#define DAVINCI_MUX_ATAEN 17
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#define DAVINCI_MUX_RGB666 22
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#define DAVINCI_MUX_RGB888 23
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#define DAVINCI_MUX_LOEEN 24
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#define DAVINCI_MUX_LFLDEN 25
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#define DAVINCI_MUX_CWEN 26
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#define DAVINCI_MUX_CFLDEN 27
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#define DAVINCI_MUX_HPIEN 29
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#define DAVINCI_MUX_1394EN 30
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#define DAVINCI_MUX_EMACEN 31
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#ifndef __INC_MACH_MUX_H
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#define __INC_MACH_MUX_H
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#define DAVINCI_MUX_LEVEL2 32
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#define DAVINCI_MUX_UART0 (DAVINCI_MUX_LEVEL2 + 0)
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#define DAVINCI_MUX_UART1 (DAVINCI_MUX_LEVEL2 + 1)
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#define DAVINCI_MUX_UART2 (DAVINCI_MUX_LEVEL2 + 2)
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#define DAVINCI_MUX_U2FLO (DAVINCI_MUX_LEVEL2 + 3)
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#define DAVINCI_MUX_PWM0 (DAVINCI_MUX_LEVEL2 + 4)
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#define DAVINCI_MUX_PWM1 (DAVINCI_MUX_LEVEL2 + 5)
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#define DAVINCI_MUX_PWM2 (DAVINCI_MUX_LEVEL2 + 6)
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#define DAVINCI_MUX_I2C (DAVINCI_MUX_LEVEL2 + 7)
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#define DAVINCI_MUX_SPI (DAVINCI_MUX_LEVEL2 + 8)
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#define DAVINCI_MUX_MSTK (DAVINCI_MUX_LEVEL2 + 9)
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#define DAVINCI_MUX_ASP (DAVINCI_MUX_LEVEL2 + 10)
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#define DAVINCI_MUX_CLK0 (DAVINCI_MUX_LEVEL2 + 16)
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#define DAVINCI_MUX_CLK1 (DAVINCI_MUX_LEVEL2 + 17)
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#define DAVINCI_MUX_TIMIN (DAVINCI_MUX_LEVEL2 + 18)
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/* System module registers */
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#define PINMUX0 0x00
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#define PINMUX1 0x04
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/* dm355 only */
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#define PINMUX2 0x08
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#define PINMUX3 0x0c
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#define PINMUX4 0x10
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#define INTMUX 0x18
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#define EVTMUX 0x1c
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extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable);
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struct mux_config {
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const char *name;
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const char *mux_reg_name;
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const unsigned char mux_reg;
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const unsigned char mask_offset;
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const unsigned char mask;
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const unsigned char mode;
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bool debug;
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};
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#endif /* __ASM_ARCH_MUX_H */
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enum davinci_dm644x_index {
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/* ATA and HDDIR functions */
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DM644X_HDIREN,
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DM644X_ATAEN,
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DM644X_ATAEN_DISABLE,
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/* HPI functions */
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DM644X_HPIEN_DISABLE,
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/* AEAW functions */
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DM644X_AEAW,
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/* Memory Stick */
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DM644X_MSTK,
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/* I2C */
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DM644X_I2C,
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/* ASP function */
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DM644X_MCBSP,
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/* UART1 */
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DM644X_UART1,
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/* UART2 */
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DM644X_UART2,
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/* PWM0 */
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DM644X_PWM0,
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/* PWM1 */
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DM644X_PWM1,
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/* PWM2 */
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DM644X_PWM2,
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/* VLYNQ function */
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DM644X_VLYNQEN,
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DM644X_VLSCREN,
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DM644X_VLYNQWD,
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/* EMAC and MDIO function */
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DM644X_EMACEN,
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/* GPIO3V[0:16] pins */
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DM644X_GPIO3V,
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/* GPIO pins */
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DM644X_GPIO0,
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DM644X_GPIO3,
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DM644X_GPIO43_44,
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DM644X_GPIO46_47,
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/* VPBE */
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DM644X_RGB666,
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/* LCD */
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DM644X_LOEEN,
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DM644X_LFLDEN,
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};
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enum davinci_dm646x_index {
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/* ATA function */
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DM646X_ATAEN,
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/* AUDIO Clock */
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DM646X_AUDCK1,
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DM646X_AUDCK0,
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/* CRGEN Control */
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DM646X_CRGMUX,
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/* VPIF Control */
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DM646X_STSOMUX_DISABLE,
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DM646X_STSIMUX_DISABLE,
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DM646X_PTSOMUX_DISABLE,
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DM646X_PTSIMUX_DISABLE,
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/* TSIF Control */
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DM646X_STSOMUX,
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DM646X_STSIMUX,
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DM646X_PTSOMUX_PARALLEL,
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DM646X_PTSIMUX_PARALLEL,
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DM646X_PTSOMUX_SERIAL,
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DM646X_PTSIMUX_SERIAL,
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};
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enum davinci_dm355_index {
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/* MMC/SD 0 */
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DM355_MMCSD0,
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/* MMC/SD 1 */
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DM355_SD1_CLK,
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DM355_SD1_CMD,
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DM355_SD1_DATA3,
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DM355_SD1_DATA2,
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DM355_SD1_DATA1,
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DM355_SD1_DATA0,
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/* I2C */
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DM355_I2C_SDA,
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DM355_I2C_SCL,
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/* ASP0 function */
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DM355_MCBSP0_BDX,
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DM355_MCBSP0_X,
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DM355_MCBSP0_BFSX,
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DM355_MCBSP0_BDR,
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DM355_MCBSP0_R,
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DM355_MCBSP0_BFSR,
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/* SPI0 */
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DM355_SPI0_SDI,
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DM355_SPI0_SDENA0,
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DM355_SPI0_SDENA1,
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/* IRQ muxing */
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DM355_INT_EDMA_CC,
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DM355_INT_EDMA_TC0_ERR,
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DM355_INT_EDMA_TC1_ERR,
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/* EDMA event muxing */
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DM355_EVT8_ASP1_TX,
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DM355_EVT9_ASP1_RX,
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DM355_EVT26_MMC0_RX,
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};
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#ifdef CONFIG_DAVINCI_MUX
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/* setup pin muxing */
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extern void davinci_mux_init(void);
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extern int davinci_mux_register(const struct mux_config *pins,
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unsigned long size);
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extern int davinci_cfg_reg(unsigned long reg_cfg);
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#else
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/* boot loader does it all (no warnings from CONFIG_DAVINCI_MUX_WARNINGS) */
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static inline void davinci_mux_init(void) {}
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static inline int davinci_mux_register(const struct mux_config *pins,
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unsigned long size) { return 0; }
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static inline int davinci_cfg_reg(unsigned long reg_cfg) { return 0; }
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#endif
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#endif /* __INC_MACH_MUX_H */
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@ -1,42 +1,103 @@
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/*
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* DaVinci pin multiplexing configurations
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* Utility to set the DAVINCI MUX register from a table in mux.h
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*
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* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
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*
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* Based on linux/arch/arm/plat-omap/mux.c:
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* Copyright (C) 2003 - 2005 Nokia Corporation
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*
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* Written by Tony Lindgren
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Copyright (C) 2008 Texas Instruments.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/spinlock.h>
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#include <mach/hardware.h>
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#include <mach/mux.h>
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/* System control register offsets */
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#define PINMUX0 0x00
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#define PINMUX1 0x04
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static const struct mux_config *mux_table;
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static unsigned long pin_table_sz;
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static DEFINE_SPINLOCK(mux_lock);
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void davinci_mux_peripheral(unsigned int mux, unsigned int enable)
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int __init davinci_mux_register(const struct mux_config *pins,
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unsigned long size)
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{
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void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
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u32 pinmux, muxreg = PINMUX0;
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mux_table = pins;
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pin_table_sz = size;
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if (mux >= DAVINCI_MUX_LEVEL2) {
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muxreg = PINMUX1;
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mux -= DAVINCI_MUX_LEVEL2;
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return 0;
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}
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/*
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* Sets the DAVINCI MUX register based on the table
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*/
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int __init_or_module davinci_cfg_reg(const unsigned long index)
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{
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static DEFINE_SPINLOCK(mux_spin_lock);
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void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
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unsigned long flags;
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const struct mux_config *cfg;
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unsigned int reg_orig = 0, reg = 0;
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unsigned int mask, warn = 0;
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if (!mux_table)
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BUG();
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if (index >= pin_table_sz) {
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printk(KERN_ERR "Invalid pin mux index: %lu (%lu)\n",
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index, pin_table_sz);
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dump_stack();
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return -ENODEV;
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}
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spin_lock(&mux_lock);
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pinmux = __raw_readl(base + muxreg);
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if (enable)
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pinmux |= (1 << mux);
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else
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pinmux &= ~(1 << mux);
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__raw_writel(pinmux, base + muxreg);
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spin_unlock(&mux_lock);
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cfg = &mux_table[index];
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if (cfg->name == NULL) {
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printk(KERN_ERR "No entry for the specified index\n");
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return -ENODEV;
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}
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/* Update the mux register in question */
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if (cfg->mask) {
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unsigned tmp1, tmp2;
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spin_lock_irqsave(&mux_spin_lock, flags);
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reg_orig = __raw_readl(base + cfg->mux_reg);
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mask = (cfg->mask << cfg->mask_offset);
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tmp1 = reg_orig & mask;
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reg = reg_orig & ~mask;
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tmp2 = (cfg->mode << cfg->mask_offset);
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reg |= tmp2;
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if (tmp1 != tmp2)
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warn = 1;
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__raw_writel(reg, base + cfg->mux_reg);
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spin_unlock_irqrestore(&mux_spin_lock, flags);
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}
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if (warn) {
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#ifdef CONFIG_DAVINCI_MUX_WARNINGS
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printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
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#endif
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}
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#ifdef CONFIG_DAVINCI_MUX_DEBUG
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if (cfg->debug || warn) {
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printk(KERN_WARNING "MUX: Setting register %s\n", cfg->name);
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printk(KERN_WARNING " %s (0x%08x) = 0x%08x -> 0x%08x\n",
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cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
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}
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#endif
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return 0;
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}
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EXPORT_SYMBOL(davinci_cfg_reg);
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@ -0,0 +1,51 @@
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/*
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* Pin-multiplex helper macros for TI DaVinci family devices
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*
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* Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Copyright (C) 2008 Texas Instruments.
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*/
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#ifndef _MACH_DAVINCI_MUX_H_
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#define _MACH_DAVINCI_MUX_H_
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#include <mach/mux.h>
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#define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
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[soc##_##desc] = { \
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.name = #desc, \
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.debug = dbg, \
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.mux_reg_name = "PINMUX"#muxreg, \
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.mux_reg = PINMUX##muxreg, \
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.mask_offset = mode_offset, \
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.mask = mode_mask, \
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.mode = mux_mode, \
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},
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#define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
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[soc##_##desc] = { \
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.name = #desc, \
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.debug = dbg, \
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.mux_reg_name = "INTMUX", \
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.mux_reg = INTMUX, \
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.mask_offset = mode_offset, \
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.mask = mode_mask, \
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.mode = mux_mode, \
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},
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#define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
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[soc##_##desc] = { \
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.name = #desc, \
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.debug = dbg, \
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.mux_reg_name = "EVTMUX", \
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.mux_reg = EVTMUX, \
|
||||
.mask_offset = mode_offset, \
|
||||
.mask = mode_mask, \
|
||||
.mode = mux_mode, \
|
||||
},
|
||||
|
||||
#endif /* _MACH_DAVINCI_MUX_H */
|
||||
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Reference in New Issue