MIPS: Probe for watch registers on cores of all vendors, not just MTI.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Acked-by: David Daney <ddaney@caviumnetworks.com>
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@ -652,21 +652,24 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
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static void __cpuinit decode_configs(struct cpuinfo_mips *c)
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static void __cpuinit decode_configs(struct cpuinfo_mips *c)
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{
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{
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int ok;
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/* MIPS32 or MIPS64 compliant CPU. */
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/* MIPS32 or MIPS64 compliant CPU. */
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c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
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c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
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MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
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MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
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c->scache.flags = MIPS_CACHE_NOT_PRESENT;
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c->scache.flags = MIPS_CACHE_NOT_PRESENT;
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/* Read Config registers. */
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ok = decode_config0(c); /* Read Config registers. */
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if (!decode_config0(c))
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BUG_ON(!ok); /* Arch spec violation! */
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return; /* actually worth a panic() */
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if (ok)
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if (!decode_config1(c))
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ok = decode_config1(c);
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return;
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if (ok)
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if (!decode_config2(c))
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ok = decode_config2(c);
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return;
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if (ok)
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if (!decode_config3(c))
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ok = decode_config3(c);
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return;
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mips_probe_watch_registers(c);
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}
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}
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#ifdef CONFIG_CPU_MIPSR2
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#ifdef CONFIG_CPU_MIPSR2
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@ -678,7 +681,6 @@ static inline void spram_config(void) {}
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static inline void cpu_probe_mips(struct cpuinfo_mips *c)
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static inline void cpu_probe_mips(struct cpuinfo_mips *c)
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{
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{
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decode_configs(c);
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decode_configs(c);
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mips_probe_watch_registers(c);
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switch (c->processor_id & 0xff00) {
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switch (c->processor_id & 0xff00) {
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case PRID_IMP_4KC:
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case PRID_IMP_4KC:
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c->cputype = CPU_4KC;
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c->cputype = CPU_4KC;
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