x86, AMD IOMMU: add comments to amd_iommu_types.h
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Cc: iommu@lists.linux-foundation.org Cc: bhavna.sarathy@amd.com Cc: robert.richter@amd.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Joerg Roedel
Ingo Molnar
parent
299a140dac
commit
5694703f14
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@ -158,78 +158,170 @@
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#define MAX_DOMAIN_ID 65536
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/*
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* This structure contains generic data for IOMMU protection domains
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* independent of their use.
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*/
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struct protection_domain {
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spinlock_t lock;
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u16 id;
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int mode;
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u64 *pt_root;
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void *priv;
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spinlock_t lock; /* mostly used to lock the page table*/
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u16 id; /* the domain id written to the device table */
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int mode; /* paging mode (0-6 levels) */
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u64 *pt_root; /* page table root pointer */
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void *priv; /* private data */
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};
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/*
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* Data container for a dma_ops specific protection domain
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*/
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struct dma_ops_domain {
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struct list_head list;
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/* generic protection domain information */
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struct protection_domain domain;
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/* size of the aperture for the mappings */
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unsigned long aperture_size;
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/* address we start to search for free addresses */
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unsigned long next_bit;
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/* address allocation bitmap */
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unsigned long *bitmap;
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/*
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* Array of PTE pages for the aperture. In this array we save all the
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* leaf pages of the domain page table used for the aperture. This way
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* we don't need to walk the page table to find a specific PTE. We can
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* just calculate its address in constant time.
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*/
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u64 **pte_pages;
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};
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/*
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* Structure where we save information about one hardware AMD IOMMU in the
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* system.
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*/
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struct amd_iommu {
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struct list_head list;
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/* locks the accesses to the hardware */
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spinlock_t lock;
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/* device id of this IOMMU */
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u16 devid;
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/*
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* Capability pointer. There could be more than one IOMMU per PCI
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* device function if there are more than one AMD IOMMU capability
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* pointers.
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*/
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u16 cap_ptr;
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/* physical address of MMIO space */
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u64 mmio_phys;
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/* virtual address of MMIO space */
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u8 *mmio_base;
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/* capabilities of that IOMMU read from ACPI */
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u32 cap;
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/* first device this IOMMU handles. read from PCI */
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u16 first_device;
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/* last device this IOMMU handles. read from PCI */
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u16 last_device;
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/* start of exclusion range of that IOMMU */
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u64 exclusion_start;
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/* length of exclusion range of that IOMMU */
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u64 exclusion_length;
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/* command buffer virtual address */
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u8 *cmd_buf;
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/* size of command buffer */
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u32 cmd_buf_size;
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/* if one, we need to send a completion wait command */
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int need_sync;
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/* default dma_ops domain for that IOMMU */
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struct dma_ops_domain *default_dom;
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};
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/*
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* List with all IOMMUs in the system. This list is not locked because it is
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* only written and read at driver initialization or suspend time
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*/
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extern struct list_head amd_iommu_list;
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/*
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* Structure defining one entry in the device table
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*/
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struct dev_table_entry {
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u32 data[8];
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};
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/*
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* One entry for unity mappings parsed out of the ACPI table.
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*/
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struct unity_map_entry {
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struct list_head list;
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/* starting device id this entry is used for (including) */
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u16 devid_start;
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/* end device id this entry is used for (including) */
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u16 devid_end;
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/* start address to unity map (including) */
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u64 address_start;
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/* end address to unity map (including) */
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u64 address_end;
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/* required protection */
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int prot;
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};
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/*
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* List of all unity mappings. It is not locked because as runtime it is only
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* read. It is created at ACPI table parsing time.
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*/
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extern struct list_head amd_iommu_unity_map;
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/* data structures for device handling */
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/*
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* Data structures for device handling
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*/
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/*
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* Device table used by hardware. Read and write accesses by software are
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* locked with the amd_iommu_pd_table lock.
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*/
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extern struct dev_table_entry *amd_iommu_dev_table;
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/*
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* Alias table to find requestor ids to device ids. Not locked because only
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* read on runtime.
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*/
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extern u16 *amd_iommu_alias_table;
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/*
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* Reverse lookup table to find the IOMMU which translates a specific device.
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*/
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extern struct amd_iommu **amd_iommu_rlookup_table;
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/* size of the dma_ops aperture as power of 2 */
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extern unsigned amd_iommu_aperture_order;
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/* largest PCI device id we expect translation requests for */
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extern u16 amd_iommu_last_bdf;
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/* data structures for protection domain handling */
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extern struct protection_domain **amd_iommu_pd_table;
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/* allocation bitmap for domain ids */
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extern unsigned long *amd_iommu_pd_alloc_bitmap;
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/* will be 1 if device isolation is enabled */
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extern int amd_iommu_isolate;
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/* takes a PCI device id and prints it out in a readable form */
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static inline void print_devid(u16 devid, int nl)
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{
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int bus = devid >> 8;
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