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[TG3]: Use constant for PHY register 0x1e. 

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Chan 2007-02-13 12:18:15 -08:00 committed by David S. Miller
parent 5129724aa5
commit 569a5df859
2 changed files with 7 additions and 4 deletions
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10
drivers/net/tg3.c
View File

@ -6594,8 +6594,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
u32 tmp;
/* Clear CRC stats. */
if (!tg3_readphy(tp, 0x1e, &tmp)) {
tg3_writephy(tp, 0x1e, tmp | 0x8000);
if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
tg3_writephy(tp, MII_TG3_TEST1,
tmp | MII_TG3_TEST1_CRC_EN);
tg3_readphy(tp, 0x14, &tmp);
}
}
@ -7419,8 +7420,9 @@ static unsigned long calc_crc_errors(struct tg3 *tp)
u32 val;
spin_lock_bh(&tp->lock);
if (!tg3_readphy(tp, 0x1e, &val)) {
tg3_writephy(tp, 0x1e, val | 0x8000);
if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
tg3_writephy(tp, MII_TG3_TEST1,
val | MII_TG3_TEST1_CRC_EN);
tg3_readphy(tp, 0x14, &val);
} else
val = 0;

1
drivers/net/tg3.h
View File

@ -1660,6 +1660,7 @@
#define MII_TG3_TEST1 0x1e
#define MII_TG3_TEST1_TRIM_EN 0x0010
#define MII_TG3_TEST1_CRC_EN 0x8000
/* There are two ways to manage the TX descriptors on the tigon3.
* Either the descriptors are in host DMA'able memory, or they