V4L/DVB (6195): Changes to support MPEG TS on VIDB
Changes to support MPEG TS on VIDB Signed-off-by: Steven Toth <stoth@hauppauge.com> Reviewed-by: Michael Krufky <mkrufky@linuxtv.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
This commit is contained in:
Steven Toth
Mauro Carvalho Chehab
parent
6f074abb62
commit
579f1163cd
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@ -100,12 +100,12 @@ struct sram_channel cx23885_sram_channels[] = {
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.cnt2_reg = DMA2_CNT2,
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},
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[SRAM_CH03] = {
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.name = "ch3",
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.cmds_start = 0x0,
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.ctrl_start = 0x0,
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.cdt = 0x0,
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.fifo_start = 0x0,
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.fifo_size = 0x0,
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.name = "TS1 B",
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.cmds_start = 0x100A0,
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.ctrl_start = 0x10780,
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.cdt = 0x10400,
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.fifo_start = 0x5000,
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.fifo_size = 0x1000,
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.ptr1_reg = DMA3_PTR1,
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.ptr2_reg = DMA3_PTR2,
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.cnt1_reg = DMA3_CNT1,
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@ -596,7 +596,7 @@ void cx23885_reset(struct cx23885_dev *dev)
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cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
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cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
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cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 128, 0);
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cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 188*4, 0);
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cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
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cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
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cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
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@ -679,6 +679,39 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
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atomic_inc(&dev->refcount);
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dev->nr = cx23885_devcount++;
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sprintf(dev->name, "cx23885[%d]", dev->nr);
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mutex_lock(&devlist);
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list_add_tail(&dev->devlist, &cx23885_devlist);
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mutex_unlock(&devlist);
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/* Configure the internal memory */
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if(dev->pci->device == 0x8880) {
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dev->bridge = CX23885_BRIDGE_887;
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dev->sram_channels = cx23887_sram_channels;
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} else
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if(dev->pci->device == 0x8852) {
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dev->bridge = CX23885_BRIDGE_885;
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dev->sram_channels = cx23885_sram_channels;
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} else
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BUG();
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dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
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__FUNCTION__, dev->bridge);
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/* board config */
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dev->board = UNSET;
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if (card[dev->nr] < cx23885_bcount)
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dev->board = card[dev->nr];
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for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
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if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
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dev->pci->subsystem_device == cx23885_subids[i].subdevice)
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dev->board = cx23885_subids[i].card;
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if (UNSET == dev->board) {
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dev->board = CX23885_BOARD_UNKNOWN;
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cx23885_card_list(dev);
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}
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dev->pci_bus = dev->pci->bus->number;
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dev->pci_slot = PCI_SLOT(dev->pci->devfn);
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dev->pci_irqmask = 0x001f00;
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@ -717,38 +750,13 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
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spin_lock_init(&dev->ts2.slock);
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dev->ts2.dev = dev;
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dev->ts2.nr = 2;
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dev->ts2.sram_chno = SRAM_CH06;
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INIT_LIST_HEAD(&dev->ts2.mpegq.active);
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INIT_LIST_HEAD(&dev->ts2.mpegq.queued);
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dev->ts2.mpegq.timeout.function = cx23885_timeout;
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dev->ts2.mpegq.timeout.data = (unsigned long)&dev->ts2;
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init_timer(&dev->ts2.mpegq.timeout);
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dev->ts2.reg_gpcnt = VID_C_GPCNT;
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dev->ts2.reg_gpcnt_ctl = VID_C_GPCNT_CTL;
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dev->ts2.reg_dma_ctl = VID_C_DMA_CTL;
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dev->ts2.reg_lngth = VID_C_LNGTH;
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dev->ts2.reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
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dev->ts2.reg_gen_ctrl = VID_C_GEN_CTL;
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dev->ts2.reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
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dev->ts2.reg_sop_status = VID_C_SOP_STATUS;
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dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
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dev->ts2.reg_vld_misc = VID_C_VLD_MISC;
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dev->ts2.reg_ts_clk_en = VID_C_TS_CLK_EN;
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dev->ts2.reg_ts_int_msk = VID_C_INT_MSK;
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// FIXME: Make this board specific
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dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
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dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
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dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
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dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
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dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
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cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper,
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dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
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sprintf(dev->name, "cx23885[%d]", dev->nr);
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if (get_resources(dev) < 0) {
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printk(KERN_ERR "CORE %s No more PCIe resources for "
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"subsystem: %04x:%04x\n",
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@ -759,46 +767,18 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
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goto fail_free;
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}
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mutex_lock(&devlist);
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list_add_tail(&dev->devlist, &cx23885_devlist);
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mutex_unlock(&devlist);
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/* PCIe stuff */
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dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
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pci_resource_len(dev->pci,0));
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dev->bmmio = (u8 __iomem *)dev->lmmio;
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/* board config */
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dev->board = UNSET;
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if (card[dev->nr] < cx23885_bcount)
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dev->board = card[dev->nr];
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for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
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if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
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dev->pci->subsystem_device == cx23885_subids[i].subdevice)
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dev->board = cx23885_subids[i].card;
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if (UNSET == dev->board) {
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dev->board = CX23885_BOARD_UNKNOWN;
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cx23885_card_list(dev);
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}
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printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
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dev->name, dev->pci->subsystem_vendor,
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dev->pci->subsystem_device, cx23885_boards[dev->board].name,
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dev->board, card[dev->nr] == dev->board ?
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"insmod option" : "autodetected");
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/* Configure the internal memory */
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if(dev->pci->device == 0x8880) {
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dev->bridge = CX23885_BRIDGE_887;
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dev->sram_channels = cx23887_sram_channels;
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} else
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if(dev->pci->device == 0x8852) {
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dev->bridge = CX23885_BRIDGE_885;
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dev->sram_channels = cx23885_sram_channels;
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}
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dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
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__FUNCTION__, dev->bridge);
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cx23885_pci_quirks(dev);
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/* init hardware */
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@ -812,6 +792,38 @@ static int cx23885_dev_setup(struct cx23885_dev *dev)
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cx23885_card_setup(dev);
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cx23885_ir_init(dev);
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switch (dev->board) {
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default:
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dev->ts2.reg_gpcnt = VID_C_GPCNT;
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dev->ts2.reg_gpcnt_ctl = VID_C_GPCNT_CTL;
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dev->ts2.reg_dma_ctl = VID_C_DMA_CTL;
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dev->ts2.reg_lngth = VID_C_LNGTH;
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dev->ts2.reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
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dev->ts2.reg_gen_ctrl = VID_C_GEN_CTL;
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dev->ts2.reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
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dev->ts2.reg_sop_status = VID_C_SOP_STATUS;
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dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
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dev->ts2.reg_vld_misc = VID_C_VLD_MISC;
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dev->ts2.reg_ts_clk_en = VID_C_TS_CLK_EN;
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dev->ts2.reg_ts_int_msk = VID_C_INT_MSK;
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dev->ts2.reg_src_sel = 0;
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// FIXME: Make this board specific
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dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
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dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
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dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
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dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
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dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
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dev->ts2.src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
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// Drive this from cards.c (portb/c) and move it outside of this switch
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dev->ts2.sram_chno = SRAM_CH06;
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}
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cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper,
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dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
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// FIXME: This should only be called if ts2 is being used, driven by cards.c
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if (cx23885_dvb_register(&dev->ts2) < 0) {
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printk(KERN_ERR "%s() Failed to register dvb adapters\n",
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__FUNCTION__);
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@ -1026,13 +1038,17 @@ static int cx23885_start_dma(struct cx23885_tsport *port,
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udelay(100);
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/* If the port supports SRC SELECT, configure it */
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if(port->reg_src_sel)
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cx_write(port->reg_src_sel, port->src_sel_val);
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cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
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cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
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cx_write(port->reg_vld_misc, 0x00);
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cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
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udelay(100);
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// NOTE: this is 2 (reserved) for portb, does it matter?
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/* reset counter to zero */
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cx_write(port->reg_gpcnt_ctl, 3);
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q->count = 1;
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@ -1047,7 +1063,7 @@ static int cx23885_start_dma(struct cx23885_tsport *port,
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cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
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break;
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default:
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printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
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BUG();
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}
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cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
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@ -68,6 +68,11 @@ enum cx23885_itype {
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CX23885_RADIO,
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};
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enum cx23885_src_sel_type {
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CX23885_SRC_SEL_EXT_656_VIDEO = 0,
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CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO
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};
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/* buffer for one video frame */
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struct cx23885_buffer {
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/* common v4l buffer stuff -- must be first */
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@ -162,6 +167,7 @@ struct cx23885_tsport {
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u32 reg_vld_misc;
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u32 reg_ts_clk_en;
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u32 reg_ts_int_msk;
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u32 reg_src_sel;
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/* Default register vals */
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int pci_irqmask;
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@ -169,6 +175,7 @@ struct cx23885_tsport {
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u32 ts_int_msk_val;
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u32 gen_ctrl_val;
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u32 ts_clk_en_val;
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u32 src_sel_val;
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};
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struct cx23885_dev {
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