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arm64: dts: qcom: msm8996: Add ufs related nodes 

Add the UFS QMP phy node and the UFS host controller node, now that we
have working UFS and the necessary clocks in place.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Bjorn Andersson 2018-05-17 23:26:38 -07:00 committed by Andy Gross
parent 242579dd08
commit 57fc67ef0d
2 changed files with 93 additions and 0 deletions
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8
arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi
View File

@ -122,6 +122,14 @@
status = "okay";
};
phy@627000 {
status = "okay";
};
ufshc@624000 {
status = "okay";
};
phy@34000 {
status = "okay";
};

85
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@ -634,6 +634,91 @@
#interrupt-cells = <4>;
};
ufsphy: phy@627000 {
compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
reg = <0x627000 0xda8>;
reg-names = "phy_mem";
#phy-cells = <0>;
vdda-phy-supply = <&pm8994_l28>;
vdda-pll-supply = <&pm8994_l12>;
vdda-phy-max-microamp = <18380>;
vdda-pll-max-microamp = <9440>;
vddp-ref-clk-supply = <&pm8994_l25>;
vddp-ref-clk-max-microamp = <100>;
vddp-ref-clk-always-on;
clock-names = "ref_clk_src", "ref_clk";
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
status = "disabled";
power-domains = <&gcc UFS_GDSC>;
};
ufshc@624000 {
compatible = "qcom,ufshc";
reg = <0x624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy>;
phy-names = "ufsphy";
vcc-supply = <&pm8994_l20>;
vccq-supply = <&pm8994_l25>;
vccq2-supply = <&pm8994_s4>;
vcc-max-microamp = <600000>;
vccq-max-microamp = <450000>;
vccq2-max-microamp = <450000>;
clock-names =
"core_clk_src",
"core_clk",
"bus_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro_src",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk";
clocks =
<&gcc UFS_AXI_CLK_SRC>,
<&gcc GCC_UFS_AXI_CLK>,
<&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
<&gcc GCC_AGGRE2_UFS_AXI_CLK>,
<&gcc GCC_UFS_AHB_CLK>,
<&gcc UFS_ICE_CORE_CLK_SRC>,
<&gcc GCC_UFS_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_ICE_CORE_CLK>,
<&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
freq-table-hz =
<100000000 200000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>,
<150000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
lanes-per-direction = <1>;
status = "disabled";
ufs_variant {
compatible = "qcom,ufs_variant";
};
};
mmcc: clock-controller@8c0000 {
compatible = "qcom,mmcc-msm8996";
#clock-cells = <1>;