Placeholder for the rk3399 watchdog pclk, some newly exported
rk3228 clockids and a small fix for the not yet used spdif to displayport clock on the rk3399. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCAAGBQJXdbFVAAoJEPOmecmc0R2B2fEH/1Gm80XZsrXPrr0kZ2cO8Zcg qUpOPJgZvEWJdG1EGzU34VAEAZP0y8sth46iypL+TP3UVf6Z9acZF2eeAbEvzdVY pM6qb0eNLdrcV+aaKhAScxjEwg5kdLxc/kuwOr9XsZwE4Wqvsbmldw5O8qEU8DAP fxdhi854hlanCVmTCfdjEpeRqv9JCejU27KttldqBC/0CwGaQwp0cUcp6Ggpv9pF deHR5BGj2cwnPR2JmNsZ9U85kgf9/7jd4PD4UXNRG/ApuwpIb0/1ulr4YquqAcDW OpdO6at9QmZItYS6byKNoAPKWoGXjmHYnjlENODQsCXoa6K8HkmDnxBtli6Iczw= =6ikd -----END PGP SIGNATURE----- Merge tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Pull rockchip clk driver updates from Heiko Stuebner: Placeholder for the rk3399 watchdog pclk, some newly exported rk3228 clockids and a small fix for the not yet used spdif to displayport clock on the rk3399. * tag 'v4.8-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix incorrect rk3399 spdif-DPTX divider bits clk: rockchip: export rk3228 MAC clocks clk: rockchip: rename rk3228 sclk_macphy_50m to sclk_mac_extclk clk: rockchip: export rk3228 audio clocks clk: rockchip: include rk3228 downstream muxes into fractional dividers clk: rockchip: fix incorrect rk3228 clock registers clk: rockchip: add clock-ids for rk3228 MAC clocks clk: rockchip: add clock-ids for rk3228 audio clocks clk: rockchip: add a dummy clock for the watchdog pclk on rk3399
This commit is contained in:
Stephen Boyd
commit
582e2405b2
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@ -151,8 +151,8 @@ PNAME(mux_uart0_p) = { "uart0_src", "uart0_frac", "xin24m" };
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PNAME(mux_uart1_p) = { "uart1_src", "uart1_frac", "xin24m" };
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PNAME(mux_uart2_p) = { "uart2_src", "uart2_frac", "xin24m" };
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PNAME(mux_sclk_macphy_50m_p) = { "ext_gmac", "phy_50m_out" };
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PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_macphy_50m" };
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PNAME(mux_sclk_mac_extclk_p) = { "ext_gmac", "phy_50m_out" };
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PNAME(mux_sclk_gmac_pre_p) = { "sclk_gmac_src", "sclk_mac_extclk" };
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PNAME(mux_sclk_macphy_p) = { "sclk_gmac_src", "ext_gmac" };
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static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
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@ -170,6 +170,34 @@ static struct rockchip_pll_clock rk3228_pll_clks[] __initdata = {
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#define DFLAGS CLK_DIVIDER_HIWORD_MASK
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#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
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static struct rockchip_clk_branch rk3228_i2s0_fracmux __initdata =
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MUX(0, "i2s0_pre", mux_i2s0_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(9), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3228_i2s1_fracmux __initdata =
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MUX(0, "i2s1_pre", mux_i2s1_pre_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(3), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3228_i2s2_fracmux __initdata =
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MUX(0, "i2s2_pre", mux_i2s2_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(16), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3228_spdif_fracmux __initdata =
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MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(6), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3228_uart0_fracmux __initdata =
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MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(13), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3228_uart1_fracmux __initdata =
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MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(14), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3228_uart2_fracmux __initdata =
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MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(15), 8, 2, MFLAGS);
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static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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/*
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* Clock-Architecture Diagram 1
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@ -335,7 +363,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(2), 6, GFLAGS),
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GATE(0, "sclk_hsadc", "ext_hsadc", 0,
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RK3288_CLKGATE_CON(10), 12, GFLAGS),
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RK2928_CLKGATE_CON(10), 12, GFLAGS),
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COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
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RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
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@ -379,22 +407,21 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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COMPOSITE(0, "i2s0_src", mux_pll_src_2plls_p, 0,
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RK2928_CLKSEL_CON(9), 15, 1, MFLAGS, 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(0), 3, GFLAGS),
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COMPOSITE_FRAC(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(8), 0,
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RK3288_CLKGATE_CON(0), 4, GFLAGS),
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COMPOSITE_NODIV(SCLK_I2S0, "sclk_i2s0", mux_i2s0_p, 0,
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RK2928_CLKSEL_CON(9), 8, 2, MFLAGS,
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COMPOSITE_FRACMUX(0, "i2s0_frac", "i2s0_src", CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(8), 0,
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RK2928_CLKGATE_CON(0), 4, GFLAGS,
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&rk3228_i2s0_fracmux),
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GATE(SCLK_I2S0, "sclk_i2s0", "i2s0_pre", CLK_SET_RATE_PARENT,
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RK2928_CLKGATE_CON(0), 5, GFLAGS),
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COMPOSITE(0, "i2s1_src", mux_pll_src_2plls_p, 0,
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RK2928_CLKSEL_CON(3), 15, 1, MFLAGS, 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(0), 10, GFLAGS),
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COMPOSITE_FRAC(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(7), 0,
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RK3288_CLKGATE_CON(0), 11, GFLAGS),
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MUX(0, "i2s1_pre", mux_i2s1_pre_p, 0,
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RK2928_CLKSEL_CON(3), 8, 2, MFLAGS),
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GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", 0,
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COMPOSITE_FRACMUX(0, "i2s1_frac", "i2s1_src", CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(7), 0,
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RK2928_CLKGATE_CON(0), 11, GFLAGS,
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&rk3228_i2s1_fracmux),
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GATE(SCLK_I2S1, "sclk_i2s1", "i2s1_pre", CLK_SET_RATE_PARENT,
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RK2928_CLKGATE_CON(0), 14, GFLAGS),
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COMPOSITE_NODIV(SCLK_I2S_OUT, "i2s_out", mux_i2s_out_p, 0,
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RK2928_CLKSEL_CON(3), 12, 1, MFLAGS,
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@ -403,21 +430,20 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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COMPOSITE(0, "i2s2_src", mux_pll_src_2plls_p, 0,
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RK2928_CLKSEL_CON(16), 15, 1, MFLAGS, 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(0), 7, GFLAGS),
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COMPOSITE_FRAC(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(30), 0,
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RK3288_CLKGATE_CON(0), 8, GFLAGS),
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COMPOSITE_NODIV(SCLK_I2S2, "sclk_i2s2", mux_i2s2_p, 0,
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RK2928_CLKSEL_CON(16), 8, 2, MFLAGS,
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COMPOSITE_FRACMUX(0, "i2s2_frac", "i2s2_src", CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(30), 0,
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RK2928_CLKGATE_CON(0), 8, GFLAGS,
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&rk3228_i2s2_fracmux),
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GATE(SCLK_I2S2, "sclk_i2s2", "i2s2_pre", CLK_SET_RATE_PARENT,
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RK2928_CLKGATE_CON(0), 9, GFLAGS),
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COMPOSITE(0, "sclk_spdif_src", mux_pll_src_2plls_p, 0,
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RK2928_CLKSEL_CON(6), 15, 1, MFLAGS, 0, 7, DFLAGS,
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RK2928_CLKGATE_CON(2), 10, GFLAGS),
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COMPOSITE_FRAC(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
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RK3288_CLKSEL_CON(20), 0,
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RK3288_CLKGATE_CON(2), 12, GFLAGS),
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MUX(SCLK_SPDIF, "sclk_spdif", mux_sclk_spdif_p, 0,
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RK2928_CLKSEL_CON(6), 8, 2, MFLAGS),
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COMPOSITE_FRACMUX(0, "spdif_frac", "sclk_spdif_src", CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(20), 0,
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RK2928_CLKGATE_CON(2), 12, GFLAGS,
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&rk3228_spdif_fracmux),
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GATE(0, "jtag", "ext_jtag", 0,
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RK2928_CLKGATE_CON(1), 3, GFLAGS),
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@ -456,45 +482,42 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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COMPOSITE(0, "uart2_src", mux_pll_src_cpll_gpll_usb480m_p,
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0, RK2928_CLKSEL_CON(15), 12, 2,
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MFLAGS, 0, 7, DFLAGS, RK2928_CLKGATE_CON(1), 12, GFLAGS),
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COMPOSITE_FRAC(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
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COMPOSITE_FRACMUX(0, "uart0_frac", "uart0_src", CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(17), 0,
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RK2928_CLKGATE_CON(1), 9, GFLAGS),
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COMPOSITE_FRAC(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
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RK2928_CLKGATE_CON(1), 9, GFLAGS,
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&rk3228_uart0_fracmux),
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COMPOSITE_FRACMUX(0, "uart1_frac", "uart1_src", CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(18), 0,
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RK2928_CLKGATE_CON(1), 11, GFLAGS),
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COMPOSITE_FRAC(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
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RK2928_CLKGATE_CON(1), 11, GFLAGS,
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&rk3228_uart1_fracmux),
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COMPOSITE_FRACMUX(0, "uart2_frac", "uart2_src", CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(19), 0,
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RK2928_CLKGATE_CON(1), 13, GFLAGS),
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MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(13), 8, 2, MFLAGS),
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MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(14), 8, 2, MFLAGS),
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MUX(SCLK_UART2, "sclk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(15), 8, 2, MFLAGS),
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RK2928_CLKGATE_CON(1), 13, GFLAGS,
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&rk3228_uart2_fracmux),
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COMPOSITE(SCLK_NANDC, "sclk_nandc", mux_pll_src_2plls_p, 0,
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RK2928_CLKSEL_CON(2), 14, 1, MFLAGS, 8, 5, DFLAGS,
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RK2928_CLKGATE_CON(1), 0, GFLAGS),
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COMPOSITE(0, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
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COMPOSITE(SCLK_MAC_SRC, "sclk_gmac_src", mux_pll_src_2plls_p, 0,
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RK2928_CLKSEL_CON(5), 7, 1, MFLAGS, 0, 5, DFLAGS,
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RK2928_CLKGATE_CON(1), 7, GFLAGS),
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MUX(0, "sclk_macphy_50m", mux_sclk_macphy_50m_p, 0,
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MUX(SCLK_MAC_EXTCLK, "sclk_mac_extclk", mux_sclk_mac_extclk_p, 0,
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RK2928_CLKSEL_CON(29), 10, 1, MFLAGS),
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MUX(0, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
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MUX(SCLK_MAC, "sclk_gmac_pre", mux_sclk_gmac_pre_p, 0,
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RK2928_CLKSEL_CON(5), 5, 1, MFLAGS),
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GATE(0, "sclk_mac_refout", "sclk_gmac_pre", 0,
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GATE(SCLK_MAC_REFOUT, "sclk_mac_refout", "sclk_gmac_pre", 0,
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RK2928_CLKGATE_CON(5), 4, GFLAGS),
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GATE(0, "sclk_mac_ref", "sclk_gmac_pre", 0,
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GATE(SCLK_MAC_REF, "sclk_mac_ref", "sclk_gmac_pre", 0,
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RK2928_CLKGATE_CON(5), 3, GFLAGS),
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GATE(0, "sclk_mac_rx", "sclk_gmac_pre", 0,
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GATE(SCLK_MAC_RX, "sclk_mac_rx", "sclk_gmac_pre", 0,
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RK2928_CLKGATE_CON(5), 5, GFLAGS),
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GATE(0, "sclk_mac_tx", "sclk_gmac_pre", 0,
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GATE(SCLK_MAC_TX, "sclk_mac_tx", "sclk_gmac_pre", 0,
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RK2928_CLKGATE_CON(5), 6, GFLAGS),
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COMPOSITE(0, "sclk_macphy", mux_sclk_macphy_p, 0,
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COMPOSITE(SCLK_MAC_PHY, "sclk_macphy", mux_sclk_macphy_p, 0,
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RK2928_CLKSEL_CON(29), 12, 1, MFLAGS, 8, 2, DFLAGS,
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RK2928_CLKGATE_CON(5), 7, GFLAGS),
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COMPOSITE(0, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
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COMPOSITE(SCLK_MAC_OUT, "sclk_gmac_out", mux_pll_src_2plls_p, 0,
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RK2928_CLKSEL_CON(5), 15, 1, MFLAGS, 8, 5, DFLAGS,
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RK2928_CLKGATE_CON(2), 2, GFLAGS),
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@ -528,7 +551,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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/* PD_PERI */
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GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
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GATE(0, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
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GATE(ACLK_GMAC, "aclk_gmac", "aclk_peri", 0, RK2928_CLKGATE_CON(11), 4, GFLAGS),
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GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 0, GFLAGS),
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GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
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@ -544,7 +567,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
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GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
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GATE(0, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
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GATE(PCLK_GMAC, "pclk_gmac", "pclk_peri", 0, RK2928_CLKGATE_CON(11), 5, GFLAGS),
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GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
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/* PD_GPU */
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@ -558,10 +581,10 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
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GATE(0, "aclk_bus_noc", "aclk_cpu", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(10), 1, GFLAGS),
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GATE(0, "hclk_rom", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
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GATE(0, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
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GATE(0, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
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GATE(0, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
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GATE(0, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
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GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 7, GFLAGS),
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GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
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GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
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GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
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GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
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GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
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GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
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@ -586,7 +586,7 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
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RK3399_CLKGATE_CON(8), 15, GFLAGS),
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COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
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RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 0, 5, DFLAGS,
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RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
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RK3399_CLKGATE_CON(10), 6, GFLAGS),
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/* i2s */
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COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
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@ -1500,6 +1500,7 @@ static void __init rk3399_clk_init(struct device_node *np)
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{
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struct rockchip_clk_provider *ctx;
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void __iomem *reg_base;
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struct clk *clk;
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reg_base = of_iomap(np, 0);
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if (!reg_base) {
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||||
|
|
@ -1514,6 +1515,14 @@ static void __init rk3399_clk_init(struct device_node *np)
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|||
return;
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||||
}
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||||
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||||
/* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
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||||
clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
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||||
if (IS_ERR(clk))
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||||
pr_warn("%s: could not register clock pclk_wdt: %ld\n",
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||||
__func__, PTR_ERR(clk));
|
||||
else
|
||||
rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
|
||||
|
||||
rockchip_clk_register_plls(ctx, rk3399_pll_clks,
|
||||
ARRAY_SIZE(rk3399_pll_clks), -1);
|
||||
|
||||
|
|
|
|||
|
|
@ -52,6 +52,15 @@
|
|||
#define SCLK_EMMC_SAMPLE 121
|
||||
#define SCLK_VOP 122
|
||||
#define SCLK_HDMI_HDCP 123
|
||||
#define SCLK_MAC_SRC 124
|
||||
#define SCLK_MAC_EXTCLK 125
|
||||
#define SCLK_MAC 126
|
||||
#define SCLK_MAC_REFOUT 127
|
||||
#define SCLK_MAC_REF 128
|
||||
#define SCLK_MAC_RX 129
|
||||
#define SCLK_MAC_TX 130
|
||||
#define SCLK_MAC_PHY 131
|
||||
#define SCLK_MAC_OUT 132
|
||||
|
||||
/* dclk gates */
|
||||
#define DCLK_VOP 190
|
||||
|
|
@ -61,6 +70,7 @@
|
|||
#define ACLK_DMAC 194
|
||||
#define ACLK_PERI 210
|
||||
#define ACLK_VOP 211
|
||||
#define ACLK_GMAC 212
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
|
|
@ -82,8 +92,13 @@
|
|||
#define PCLK_PERI 363
|
||||
#define PCLK_HDMI_CTRL 364
|
||||
#define PCLK_HDMI_PHY 365
|
||||
#define PCLK_GMAC 367
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_I2S0_8CH 442
|
||||
#define HCLK_I2S1_8CH 443
|
||||
#define HCLK_I2S2_2CH 444
|
||||
#define HCLK_SPDIF_8CH 445
|
||||
#define HCLK_VOP 452
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
|
|
|
|||
Loading…
Reference in New Issue