EDAC/amd64: Read back the scrub rate PCI register on F15h
[ Upstream commitee470bb25d
] Commit:da92110dfd
("EDAC, amd64_edac: Extend scrub rate support to F15hM60h") added support for F15h, model 0x60 CPUs but in doing so, missed to read back SCRCTRL PCI config register on F15h CPUs which are *not* model 0x60. Add that read so that doing $ cat /sys/devices/system/edac/mc/mc0/sdram_scrub_rate can show the previously set DRAM scrub rate. Fixes:da92110dfd
("EDAC, amd64_edac: Extend scrub rate support to F15hM60h") Reported-by: Anders Andersson <pipatron@gmail.com> Signed-off-by: Borislav Petkov <bp@suse.de> Cc: <stable@vger.kernel.org> #v4.4.. Link: https://lkml.kernel.org/r/CAKkunMbNWppx_i6xSdDHLseA2QQmGJqj_crY=NF-GZML5np4Vw@mail.gmail.com Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -265,6 +265,8 @@ static int get_scrub_rate(struct mem_ctl_info *mci)
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if (pvt->model == 0x60)
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amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
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else
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amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
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break;
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case 0x17:
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