[TG3]: Refine DMA boundary setting.
Extract DMA boundary bit selection into a seperate function, tg3_calc_dma_bndry(). Call this from tg3_test_dma(). Make DMA test more reliable by using no DMA boundry setting during the test. If the test passes, then use the setting we selected before the test. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Michael Chan <mchan@broadcom.com>
This commit is contained in:
David S. Miller
parent
15f9850d3c
commit
59e6b43432
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@ -8775,6 +8775,146 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
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return 0;
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}
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#define BOUNDARY_SINGLE_CACHELINE 1
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#define BOUNDARY_MULTI_CACHELINE 2
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static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
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{
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int cacheline_size;
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u8 byte;
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int goal;
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pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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/* On 5703 and later chips, the boundary bits have no
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* effect.
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
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!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
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goto out;
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#if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
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goal = BOUNDARY_MULTI_CACHELINE;
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#else
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#if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
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goal = BOUNDARY_SINGLE_CACHELINE;
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#else
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goal = 0;
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#endif
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#endif
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if (!goal)
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goto out;
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/* PCI controllers on most RISC systems tend to disconnect
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* when a device tries to burst across a cache-line boundary.
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* Therefore, letting tg3 do so just wastes PCI bandwidth.
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*
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* Unfortunately, for PCI-E there are only limited
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* write-side controls for this, and thus for reads
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* we will still get the disconnects. We'll also waste
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* these PCI cycles for both read and write for chips
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* other than 5700 and 5701 which do not implement the
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* boundary bits.
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*/
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if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
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!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
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switch (cacheline_size) {
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case 16:
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case 32:
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case 64:
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case 128:
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if (goal == BOUNDARY_SINGLE_CACHELINE) {
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val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
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DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
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} else {
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val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
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DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
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}
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break;
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case 256:
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val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
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DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
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break;
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default:
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val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
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DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
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break;
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};
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} else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
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switch (cacheline_size) {
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case 16:
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case 32:
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case 64:
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if (goal == BOUNDARY_SINGLE_CACHELINE) {
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val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
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val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
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break;
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}
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/* fallthrough */
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case 128:
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default:
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val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
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val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
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break;
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};
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} else {
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switch (cacheline_size) {
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case 16:
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if (goal == BOUNDARY_SINGLE_CACHELINE) {
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val |= (DMA_RWCTRL_READ_BNDRY_16 |
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DMA_RWCTRL_WRITE_BNDRY_16);
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break;
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}
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/* fallthrough */
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case 32:
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if (goal == BOUNDARY_SINGLE_CACHELINE) {
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val |= (DMA_RWCTRL_READ_BNDRY_32 |
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DMA_RWCTRL_WRITE_BNDRY_32);
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break;
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}
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/* fallthrough */
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case 64:
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if (goal == BOUNDARY_SINGLE_CACHELINE) {
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val |= (DMA_RWCTRL_READ_BNDRY_64 |
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DMA_RWCTRL_WRITE_BNDRY_64);
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break;
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}
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/* fallthrough */
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case 128:
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if (goal == BOUNDARY_SINGLE_CACHELINE) {
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val |= (DMA_RWCTRL_READ_BNDRY_128 |
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DMA_RWCTRL_WRITE_BNDRY_128);
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break;
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}
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/* fallthrough */
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case 256:
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val |= (DMA_RWCTRL_READ_BNDRY_256 |
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DMA_RWCTRL_WRITE_BNDRY_256);
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break;
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case 512:
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val |= (DMA_RWCTRL_READ_BNDRY_512 |
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DMA_RWCTRL_WRITE_BNDRY_512);
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break;
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case 1024:
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default:
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val |= (DMA_RWCTRL_READ_BNDRY_1024 |
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DMA_RWCTRL_WRITE_BNDRY_1024);
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break;
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};
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}
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out:
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return val;
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}
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static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
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{
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struct tg3_internal_buffer_desc test_desc;
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@ -8861,7 +9001,7 @@ static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dm
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static int __devinit tg3_test_dma(struct tg3 *tp)
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{
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dma_addr_t buf_dma;
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u32 *buf;
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u32 *buf, saved_dma_rwctrl;
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int ret;
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buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
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@ -8873,46 +9013,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
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tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
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(0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
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#ifndef CONFIG_X86
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{
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u8 byte;
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int cacheline_size;
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pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
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if (byte == 0)
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cacheline_size = 1024;
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else
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cacheline_size = (int) byte * 4;
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switch (cacheline_size) {
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case 16:
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case 32:
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case 64:
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case 128:
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if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
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!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
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tp->dma_rwctrl |=
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DMA_RWCTRL_WRITE_BNDRY_384_PCIX;
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break;
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} else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
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tp->dma_rwctrl &=
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~(DMA_RWCTRL_PCI_WRITE_CMD);
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tp->dma_rwctrl |=
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DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
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break;
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}
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/* fallthrough */
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case 256:
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if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
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!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
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tp->dma_rwctrl |=
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DMA_RWCTRL_WRITE_BNDRY_256;
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else if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
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tp->dma_rwctrl |=
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DMA_RWCTRL_WRITE_BNDRY_256_PCIX;
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};
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}
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#endif
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tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
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if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
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/* DMA read watermark not used on PCIE */
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@ -8931,7 +9032,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
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if (ccval == 0x6 || ccval == 0x7)
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tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
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/* Set bit 23 to renable PCIX hw bug fix */
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/* Set bit 23 to enable PCIX hw bug fix */
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tp->dma_rwctrl |= 0x009f0000;
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} else {
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tp->dma_rwctrl |= 0x001b000f;
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@ -8972,6 +9073,13 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
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goto out;
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/* It is best to perform DMA test with maximum write burst size
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* to expose the 5700/5701 write DMA bug.
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*/
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saved_dma_rwctrl = tp->dma_rwctrl;
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tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
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tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
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while (1) {
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u32 *p = buf, i;
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@ -9010,8 +9118,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
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if (p[i] == i)
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continue;
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if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) ==
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DMA_RWCTRL_WRITE_BNDRY_DISAB) {
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if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
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DMA_RWCTRL_WRITE_BNDRY_16) {
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tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
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tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
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tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
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break;
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@ -9028,6 +9137,14 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
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break;
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}
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}
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if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
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DMA_RWCTRL_WRITE_BNDRY_16) {
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/* DMA test passed without adjusting DMA boundary,
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* just restore the calculated DMA boundary
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*/
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tp->dma_rwctrl = saved_dma_rwctrl;
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tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
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}
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out:
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pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
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@ -9429,6 +9546,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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(tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
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(tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
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(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
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printk(KERN_INFO "%s: dma_rwctrl[%08x]\n",
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dev->name, tp->dma_rwctrl);
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return 0;
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