lguest: support backdoor window.
The VIRTIO_PCI_CAP_PCI_CFG in the PCI virtio 1.0 spec allows access to the BAR registers without mapping them. This is a compulsory feature, and we implement it here. There are some subtleties involving access widths which we should note: 4.1.4.7.1 Device Requirements: PCI configuration access capability ... Upon detecting driver write access to pci_cfg_data, the device MUST execute a write access at offset cap.offset at BAR selected by cap.bar using the first cap.length bytes from pci_cfg_data. Upon detecting driver read access to pci_cfg_data, the device MUST execute a read access of length cap.length at offset cap.offset at BAR selected by cap.bar and store the first cap.length bytes in pci_cfg_data. So, for a write, we copy into the pci_cfg_data window, then write from there out to the BAR. This works correctly if cap.length != width of write. Similarly, for a read, we read into window from the BAR then read the value from there. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
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@ -156,7 +156,6 @@ struct pci_config {
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struct virtio_pci_notify_cap notify;
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struct virtio_pci_notify_cap notify;
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struct virtio_pci_cap isr;
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struct virtio_pci_cap isr;
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struct virtio_pci_cap device;
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struct virtio_pci_cap device;
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/* FIXME: Implement this! */
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struct virtio_pci_cfg_cap cfg_access;
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struct virtio_pci_cfg_cap cfg_access;
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};
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};
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@ -1184,6 +1183,36 @@ static struct device *dev_and_reg(u32 *reg)
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return find_pci_device(pci_config_addr.bits.devnum);
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return find_pci_device(pci_config_addr.bits.devnum);
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}
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}
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/*
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* We can get invalid combinations of values while they're writing, so we
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* only fault if they try to write with some invalid bar/offset/length.
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*/
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static bool valid_bar_access(struct device *d,
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struct virtio_pci_cfg_cap *cfg_access)
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{
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/* We only have 1 bar (BAR0) */
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if (cfg_access->cap.bar != 0)
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return false;
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/* Check it's within BAR0. */
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if (cfg_access->cap.offset >= d->mmio_size
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|| cfg_access->cap.offset + cfg_access->cap.length > d->mmio_size)
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return false;
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/* Check length is 1, 2 or 4. */
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if (cfg_access->cap.length != 1
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&& cfg_access->cap.length != 2
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&& cfg_access->cap.length != 4)
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return false;
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/* Offset must be multiple of length */
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if (cfg_access->cap.offset % cfg_access->cap.length != 0)
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return false;
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/* Return pointer into word in BAR0. */
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return true;
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}
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/* Is this accessing the PCI config address port?. */
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/* Is this accessing the PCI config address port?. */
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static bool is_pci_addr_port(u16 port)
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static bool is_pci_addr_port(u16 port)
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{
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{
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@ -1215,6 +1244,8 @@ static bool is_pci_data_port(u16 port)
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return port >= PCI_CONFIG_DATA && port < PCI_CONFIG_DATA + 4;
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return port >= PCI_CONFIG_DATA && port < PCI_CONFIG_DATA + 4;
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}
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}
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static void emulate_mmio_write(struct device *d, u32 off, u32 val, u32 mask);
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static bool pci_data_iowrite(u16 port, u32 mask, u32 val)
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static bool pci_data_iowrite(u16 port, u32 mask, u32 val)
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{
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{
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u32 reg, portoff;
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u32 reg, portoff;
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@ -1255,12 +1286,53 @@ static bool pci_data_iowrite(u16 port, u32 mask, u32 val)
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&& mask == 0xFFFF) {
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&& mask == 0xFFFF) {
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/* Ignore command writes. */
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/* Ignore command writes. */
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return true;
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return true;
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} else if (&d->config_words[reg]
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== (void *)&d->config.cfg_access.cap.bar
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|| &d->config_words[reg]
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== &d->config.cfg_access.cap.length
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|| &d->config_words[reg]
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== &d->config.cfg_access.cap.offset) {
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/*
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* The VIRTIO_PCI_CAP_PCI_CFG capability
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* provides a backdoor to access the MMIO
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* regions without mapping them. Weird, but
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* useful.
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*/
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iowrite(portoff, val, mask, &d->config_words[reg]);
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return true;
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} else if (&d->config_words[reg] == &d->config.cfg_access.window) {
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u32 write_mask;
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/* Must be bar 0 */
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if (!valid_bar_access(d, &d->config.cfg_access))
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return false;
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/* First copy what they wrote into the window */
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iowrite(portoff, val, mask, &d->config.cfg_access.window);
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/*
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* Now emulate a write. The mask we use is set by
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* len, *not* this write!
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*/
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write_mask = (1ULL<<(8*d->config.cfg_access.cap.length)) - 1;
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verbose("Window writing %#x/%#x to bar %u, offset %u len %u\n",
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d->config.cfg_access.window, write_mask,
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d->config.cfg_access.cap.bar,
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d->config.cfg_access.cap.offset,
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d->config.cfg_access.cap.length);
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emulate_mmio_write(d, d->config.cfg_access.cap.offset,
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d->config.cfg_access.window, write_mask);
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return true;
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}
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}
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/* Complain about other writes. */
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/* Complain about other writes. */
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return false;
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return false;
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}
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}
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static u32 emulate_mmio_read(struct device *d, u32 off, u32 mask);
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static void pci_data_ioread(u16 port, u32 mask, u32 *val)
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static void pci_data_ioread(u16 port, u32 mask, u32 *val)
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{
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{
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u32 reg;
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u32 reg;
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@ -1268,6 +1340,33 @@ static void pci_data_ioread(u16 port, u32 mask, u32 *val)
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if (!d)
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if (!d)
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return;
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return;
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/* Read through the PCI MMIO access window is special */
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if (&d->config_words[reg] == &d->config.cfg_access.window) {
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u32 read_mask;
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/* Must be bar 0 */
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if (!valid_bar_access(d, &d->config.cfg_access))
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errx(1, "Invalid cfg_access to bar%u, offset %u len %u",
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d->config.cfg_access.cap.bar,
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d->config.cfg_access.cap.offset,
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d->config.cfg_access.cap.length);
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/*
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* Read into the window. The mask we use is set by
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* len, *not* this read!
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*/
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read_mask = (1ULL<<(8*d->config.cfg_access.cap.length))-1;
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d->config.cfg_access.window
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= emulate_mmio_read(d,
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d->config.cfg_access.cap.offset,
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read_mask);
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verbose("Window read %#x/%#x from bar %u, offset %u len %u\n",
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d->config.cfg_access.window, read_mask,
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d->config.cfg_access.cap.bar,
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d->config.cfg_access.cap.offset,
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d->config.cfg_access.cap.length);
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}
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ioread(port - PCI_CONFIG_DATA, d->config_words[reg], mask, val);
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ioread(port - PCI_CONFIG_DATA, d->config_words[reg], mask, val);
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}
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}
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