powerpc, hw_breakpoints: Implement hw_breakpoints for 64-bit server processors
Implement perf-events based hw-breakpoint interfaces for PowerPC 64-bit server (Book III S) processors. This allows access to a given location to be used as an event that can be counted or profiled by the perf_events subsystem. This is done using the DABR (data breakpoint register), which can also be used for process debugging via ptrace. When perf_event hw_breakpoint support is configured in, the perf_event subsystem manages the DABR and arbitrates access to it, and ptrace then creates a perf_event when it is requested to set a data breakpoint. [Adopted suggestions from Paul Mackerras <paulus@samba.org> to - emulate_step() all system-wide breakpoints and single-step only the per-task breakpoints - perform arch-specific cleanup before unregistration through arch_unregister_hw_breakpoint() ] Signed-off-by: K.Prasad <prasad@linux.vnet.ibm.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
parent
f7136c5150
commit
5aae8a5370
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@ -141,6 +141,7 @@ config PPC
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select GENERIC_ATOMIC64 if PPC32
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select HAVE_PERF_EVENTS
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select HAVE_REGS_AND_STACK_ACCESS_API
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select HAVE_HW_BREAKPOINT if PERF_EVENTS && PPC_BOOK3S_64
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config EARLY_PRINTK
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bool
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@ -517,6 +517,10 @@ static inline int cpu_has_feature(unsigned long feature)
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& feature);
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}
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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#define HBP_NUM 1
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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#endif /* !__ASSEMBLY__ */
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#endif /* __KERNEL__ */
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@ -0,0 +1,73 @@
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/*
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* PowerPC BookIII S hardware breakpoint definitions
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2010, IBM Corporation.
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* Author: K.Prasad <prasad@linux.vnet.ibm.com>
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*
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*/
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#ifndef _PPC_BOOK3S_64_HW_BREAKPOINT_H
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#define _PPC_BOOK3S_64_HW_BREAKPOINT_H
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#ifdef __KERNEL__
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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struct arch_hw_breakpoint {
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u8 len; /* length of the target data symbol */
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int type;
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unsigned long address;
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};
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#include <linux/kdebug.h>
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#include <asm/reg.h>
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#include <asm/system.h>
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static inline int hw_breakpoint_slots(int type)
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{
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return HBP_NUM;
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}
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struct perf_event;
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struct pmu;
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struct perf_sample_data;
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#define HW_BREAKPOINT_ALIGN 0x7
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/* Maximum permissible length of any HW Breakpoint */
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#define HW_BREAKPOINT_LEN 0x8
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extern int arch_bp_generic_fields(int type, int *gen_bp_type);
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extern int arch_check_bp_in_kernelspace(struct perf_event *bp);
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extern int arch_validate_hwbkpt_settings(struct perf_event *bp);
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extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
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unsigned long val, void *data);
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int arch_install_hw_breakpoint(struct perf_event *bp);
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void arch_uninstall_hw_breakpoint(struct perf_event *bp);
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void hw_breakpoint_pmu_read(struct perf_event *bp);
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extern void flush_ptrace_hw_breakpoint(struct task_struct *tsk);
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extern struct pmu perf_ops_bp;
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extern void ptrace_triggered(struct perf_event *bp, int nmi,
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struct perf_sample_data *data, struct pt_regs *regs);
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static inline void hw_breakpoint_disable(void)
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{
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set_dabr(0);
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}
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#else /* CONFIG_HAVE_HW_BREAKPOINT */
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static inline void hw_breakpoint_disable(void) { }
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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#endif /* __KERNEL__ */
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#endif /* _PPC_BOOK3S_64_HW_BREAKPOINT_H */
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@ -209,6 +209,14 @@ struct thread_struct {
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#ifdef CONFIG_PPC64
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unsigned long start_tb; /* Start purr when proc switched in */
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unsigned long accum_tb; /* Total accumilated purr for process */
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#ifdef CONFIG_HAVE_HW_BREAKPOINT
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struct perf_event *ptrace_bps[HBP_NUM];
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/*
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* Helps identify source of single-step exception and subsequent
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* hw-breakpoint enablement
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*/
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struct perf_event *last_hit_ubp;
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#endif /* CONFIG_HAVE_HW_BREAKPOINT */
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#endif
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unsigned long dabr; /* Data address breakpoint register */
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#ifdef CONFIG_ALTIVEC
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@ -34,6 +34,7 @@ obj-y += vdso32/
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obj-$(CONFIG_PPC64) += setup_64.o sys_ppc32.o \
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signal_64.o ptrace32.o \
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paca.o nvram_64.o firmware.o
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obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
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obj-$(CONFIG_PPC_BOOK3S_64) += cpu_setup_ppc970.o cpu_setup_pa6t.o
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obj64-$(CONFIG_RELOCATABLE) += reloc_64.o
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obj-$(CONFIG_PPC_BOOK3E_64) += exceptions-64e.o
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@ -828,6 +828,7 @@ END_FW_FTR_SECTION_IFCLR(FW_FEATURE_ISERIES)
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/* We have a data breakpoint exception - handle it */
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handle_dabr_fault:
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bl .save_nvgprs
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ld r4,_DAR(r1)
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ld r5,_DSISR(r1)
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addi r3,r1,STACK_FRAME_OVERHEAD
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@ -0,0 +1,325 @@
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/*
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* HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
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* using the CPU's debug registers. Derived from
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* "arch/x86/kernel/hw_breakpoint.c"
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright 2010 IBM Corporation
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* Author: K.Prasad <prasad@linux.vnet.ibm.com>
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*
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*/
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#include <linux/hw_breakpoint.h>
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#include <linux/notifier.h>
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#include <linux/kprobes.h>
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#include <linux/percpu.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/hw_breakpoint.h>
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#include <asm/processor.h>
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#include <asm/sstep.h>
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#include <asm/uaccess.h>
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/*
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* Stores the breakpoints currently in use on each breakpoint address
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* register for every cpu
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*/
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static DEFINE_PER_CPU(struct perf_event *, bp_per_reg);
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/*
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* Install a perf counter breakpoint.
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*
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* We seek a free debug address register and use it for this
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* breakpoint.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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int arch_install_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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struct perf_event **slot = &__get_cpu_var(bp_per_reg);
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*slot = bp;
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/*
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* Do not install DABR values if the instruction must be single-stepped.
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* If so, DABR will be populated in single_step_dabr_instruction().
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*/
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if (current->thread.last_hit_ubp != bp)
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set_dabr(info->address | info->type | DABR_TRANSLATION);
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return 0;
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}
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/*
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* Uninstall the breakpoint contained in the given counter.
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*
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* First we search the debug address register it uses and then we disable
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* it.
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*
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* Atomic: we hold the counter->ctx->lock and we only handle variables
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* and registers local to this cpu.
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*/
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void arch_uninstall_hw_breakpoint(struct perf_event *bp)
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{
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struct perf_event **slot = &__get_cpu_var(bp_per_reg);
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if (*slot != bp) {
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WARN_ONCE(1, "Can't find the breakpoint");
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return;
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}
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*slot = NULL;
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set_dabr(0);
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}
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/*
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* Perform cleanup of arch-specific counters during unregistration
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* of the perf-event
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*/
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void arch_unregister_hw_breakpoint(struct perf_event *bp)
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{
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/*
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* If the breakpoint is unregistered between a hw_breakpoint_handler()
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* and the single_step_dabr_instruction(), then cleanup the breakpoint
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* restoration variables to prevent dangling pointers.
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*/
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if (bp->ctx->task)
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bp->ctx->task->thread.last_hit_ubp = NULL;
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}
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/*
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* Check for virtual address in kernel space.
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*/
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int arch_check_bp_in_kernelspace(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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return is_kernel_addr(info->address);
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}
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int arch_bp_generic_fields(int type, int *gen_bp_type)
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{
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switch (type) {
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case DABR_DATA_READ:
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*gen_bp_type = HW_BREAKPOINT_R;
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break;
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case DABR_DATA_WRITE:
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*gen_bp_type = HW_BREAKPOINT_W;
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break;
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case (DABR_DATA_WRITE | DABR_DATA_READ):
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*gen_bp_type = (HW_BREAKPOINT_W | HW_BREAKPOINT_R);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* Validate the arch-specific HW Breakpoint register settings
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*/
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int arch_validate_hwbkpt_settings(struct perf_event *bp)
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{
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int ret = -EINVAL;
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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if (!bp)
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return ret;
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switch (bp->attr.bp_type) {
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case HW_BREAKPOINT_R:
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info->type = DABR_DATA_READ;
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break;
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case HW_BREAKPOINT_W:
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info->type = DABR_DATA_WRITE;
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break;
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case HW_BREAKPOINT_R | HW_BREAKPOINT_W:
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info->type = (DABR_DATA_READ | DABR_DATA_WRITE);
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break;
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default:
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return ret;
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}
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info->address = bp->attr.bp_addr;
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info->len = bp->attr.bp_len;
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/*
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* Since breakpoint length can be a maximum of HW_BREAKPOINT_LEN(8)
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* and breakpoint addresses are aligned to nearest double-word
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* HW_BREAKPOINT_ALIGN by rounding off to the lower address, the
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* 'symbolsize' should satisfy the check below.
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*/
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if (info->len >
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(HW_BREAKPOINT_LEN - (info->address & HW_BREAKPOINT_ALIGN)))
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return -EINVAL;
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return 0;
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}
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/*
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* Handle debug exception notifications.
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*/
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int __kprobes hw_breakpoint_handler(struct die_args *args)
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{
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bool is_ptrace_bp = false;
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int rc = NOTIFY_STOP;
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struct perf_event *bp;
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struct pt_regs *regs = args->regs;
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int stepped = 1;
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struct arch_hw_breakpoint *info;
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unsigned int instr;
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/* Disable breakpoints during exception handling */
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set_dabr(0);
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/*
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* The counter may be concurrently released but that can only
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* occur from a call_rcu() path. We can then safely fetch
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* the breakpoint, use its callback, touch its counter
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* while we are in an rcu_read_lock() path.
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*/
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rcu_read_lock();
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bp = __get_cpu_var(bp_per_reg);
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if (!bp)
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goto out;
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info = counter_arch_bp(bp);
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is_ptrace_bp = (bp->overflow_handler == ptrace_triggered) ?
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true : false;
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/*
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* Return early after invoking user-callback function without restoring
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* DABR if the breakpoint is from ptrace which always operates in
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* one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
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* generated in do_dabr().
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*/
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if (is_ptrace_bp) {
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perf_bp_event(bp, regs);
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rc = NOTIFY_DONE;
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goto out;
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}
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/* Do not emulate user-space instructions, instead single-step them */
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if (user_mode(regs)) {
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bp->ctx->task->thread.last_hit_ubp = bp;
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regs->msr |= MSR_SE;
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goto out;
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}
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stepped = 0;
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instr = 0;
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if (!__get_user_inatomic(instr, (unsigned int *) regs->nip))
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stepped = emulate_step(regs, instr);
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/*
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* emulate_step() could not execute it. We've failed in reliably
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* handling the hw-breakpoint. Unregister it and throw a warning
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* message to let the user know about it.
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*/
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if (!stepped) {
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WARN(1, "Unable to handle hardware breakpoint. Breakpoint at "
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"0x%lx will be disabled.", info->address);
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perf_event_disable(bp);
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goto out;
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}
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/*
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* As a policy, the callback is invoked in a 'trigger-after-execute'
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* fashion
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*/
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perf_bp_event(bp, regs);
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set_dabr(info->address | info->type | DABR_TRANSLATION);
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out:
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rcu_read_unlock();
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return rc;
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}
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/*
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* Handle single-step exceptions following a DABR hit.
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*/
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int __kprobes single_step_dabr_instruction(struct die_args *args)
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{
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struct pt_regs *regs = args->regs;
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struct perf_event *bp = NULL;
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struct arch_hw_breakpoint *bp_info;
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bp = current->thread.last_hit_ubp;
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/*
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* Check if we are single-stepping as a result of a
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* previous HW Breakpoint exception
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*/
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if (!bp)
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return NOTIFY_DONE;
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bp_info = counter_arch_bp(bp);
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/*
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* We shall invoke the user-defined callback function in the single
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* stepping handler to confirm to 'trigger-after-execute' semantics
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*/
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perf_bp_event(bp, regs);
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/*
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* Do not disable MSR_SE if the process was already in
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* single-stepping mode.
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*/
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if (!test_thread_flag(TIF_SINGLESTEP))
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regs->msr &= ~MSR_SE;
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set_dabr(bp_info->address | bp_info->type | DABR_TRANSLATION);
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current->thread.last_hit_ubp = NULL;
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return NOTIFY_STOP;
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}
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/*
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* Handle debug exception notifications.
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*/
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int __kprobes hw_breakpoint_exceptions_notify(
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struct notifier_block *unused, unsigned long val, void *data)
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{
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int ret = NOTIFY_DONE;
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switch (val) {
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case DIE_DABR_MATCH:
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ret = hw_breakpoint_handler(data);
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break;
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case DIE_SSTEP:
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ret = single_step_dabr_instruction(data);
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break;
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}
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return ret;
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}
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/*
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* Release the user breakpoints used by ptrace
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*/
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void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
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{
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struct thread_struct *t = &tsk->thread;
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unregister_hw_breakpoint(t->ptrace_bps[0]);
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t->ptrace_bps[0] = NULL;
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}
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void hw_breakpoint_pmu_read(struct perf_event *bp)
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{
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/* TODO */
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}
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@ -25,6 +25,7 @@
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#include <asm/sections.h> /* _end */
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#include <asm/prom.h>
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#include <asm/smp.h>
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#include <asm/hw_breakpoint.h>
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int default_machine_kexec_prepare(struct kimage *image)
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{
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|
@ -165,6 +166,7 @@ static void kexec_smp_down(void *arg)
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while(kexec_all_irq_disabled == 0)
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cpu_relax();
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mb(); /* make sure all irqs are disabled before this */
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hw_breakpoint_disable();
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/*
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* Now every CPU has IRQs off, we can clear out any pending
|
||||
* IPIs and be sure that no more will come in after this.
|
||||
|
@ -180,6 +182,7 @@ static void kexec_prepare_cpus_wait(int wait_state)
|
|||
{
|
||||
int my_cpu, i, notified=-1;
|
||||
|
||||
hw_breakpoint_disable();
|
||||
my_cpu = get_cpu();
|
||||
/* Make sure each CPU has atleast made it to the state we need */
|
||||
for (i=0; i < NR_CPUS; i++) {
|
||||
|
|
|
@ -37,6 +37,7 @@
|
|||
#include <linux/kernel_stat.h>
|
||||
#include <linux/personality.h>
|
||||
#include <linux/random.h>
|
||||
#include <linux/hw_breakpoint.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/uaccess.h>
|
||||
|
@ -462,8 +463,14 @@ struct task_struct *__switch_to(struct task_struct *prev,
|
|||
#ifdef CONFIG_PPC_ADV_DEBUG_REGS
|
||||
switch_booke_debug_regs(&new->thread);
|
||||
#else
|
||||
/*
|
||||
* For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
|
||||
* schedule DABR
|
||||
*/
|
||||
#ifndef CONFIG_HAVE_HW_BREAKPOINT
|
||||
if (unlikely(__get_cpu_var(current_dabr) != new->thread.dabr))
|
||||
set_dabr(new->thread.dabr);
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
||||
#endif
|
||||
|
||||
|
||||
|
@ -642,7 +649,11 @@ void flush_thread(void)
|
|||
{
|
||||
discard_lazy_cpu_state();
|
||||
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINTS
|
||||
flush_ptrace_hw_breakpoint(current);
|
||||
#else /* CONFIG_HAVE_HW_BREAKPOINTS */
|
||||
set_debug_reg_defaults(¤t->thread);
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINTS */
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -660,6 +671,9 @@ void prepare_to_copy(struct task_struct *tsk)
|
|||
flush_altivec_to_thread(current);
|
||||
flush_vsx_to_thread(current);
|
||||
flush_spe_to_thread(current);
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
flush_ptrace_hw_breakpoint(tsk);
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -32,6 +32,8 @@
|
|||
#ifdef CONFIG_PPC32
|
||||
#include <linux/module.h>
|
||||
#endif
|
||||
#include <linux/hw_breakpoint.h>
|
||||
#include <linux/perf_event.h>
|
||||
|
||||
#include <asm/uaccess.h>
|
||||
#include <asm/page.h>
|
||||
|
@ -866,9 +868,34 @@ void user_disable_single_step(struct task_struct *task)
|
|||
clear_tsk_thread_flag(task, TIF_SINGLESTEP);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
void ptrace_triggered(struct perf_event *bp, int nmi,
|
||||
struct perf_sample_data *data, struct pt_regs *regs)
|
||||
{
|
||||
struct perf_event_attr attr;
|
||||
|
||||
/*
|
||||
* Disable the breakpoint request here since ptrace has defined a
|
||||
* one-shot behaviour for breakpoint exceptions in PPC64.
|
||||
* The SIGTRAP signal is generated automatically for us in do_dabr().
|
||||
* We don't have to do anything about that here
|
||||
*/
|
||||
attr = bp->attr;
|
||||
attr.disabled = true;
|
||||
modify_user_hw_breakpoint(bp, &attr);
|
||||
}
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
||||
|
||||
int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
|
||||
unsigned long data)
|
||||
{
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
int ret;
|
||||
struct thread_struct *thread = &(task->thread);
|
||||
struct perf_event *bp;
|
||||
struct perf_event_attr attr;
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
||||
|
||||
/* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
|
||||
* For embedded processors we support one DAC and no IAC's at the
|
||||
* moment.
|
||||
|
@ -896,6 +923,43 @@ int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
|
|||
/* Ensure breakpoint translation bit is set */
|
||||
if (data && !(data & DABR_TRANSLATION))
|
||||
return -EIO;
|
||||
#ifdef CONFIG_HAVE_HW_BREAKPOINT
|
||||
bp = thread->ptrace_bps[0];
|
||||
if ((!data) || !(data & (DABR_DATA_WRITE | DABR_DATA_READ))) {
|
||||
if (bp) {
|
||||
unregister_hw_breakpoint(bp);
|
||||
thread->ptrace_bps[0] = NULL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
if (bp) {
|
||||
attr = bp->attr;
|
||||
attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
|
||||
arch_bp_generic_fields(data &
|
||||
(DABR_DATA_WRITE | DABR_DATA_READ),
|
||||
&attr.bp_type);
|
||||
ret = modify_user_hw_breakpoint(bp, &attr);
|
||||
if (ret)
|
||||
return ret;
|
||||
thread->ptrace_bps[0] = bp;
|
||||
thread->dabr = data;
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Create a new breakpoint request if one doesn't exist already */
|
||||
hw_breakpoint_init(&attr);
|
||||
attr.bp_addr = data & ~HW_BREAKPOINT_ALIGN;
|
||||
arch_bp_generic_fields(data & (DABR_DATA_WRITE | DABR_DATA_READ),
|
||||
&attr.bp_type);
|
||||
|
||||
thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
|
||||
ptrace_triggered, task);
|
||||
if (IS_ERR(bp)) {
|
||||
thread->ptrace_bps[0] = NULL;
|
||||
return PTR_ERR(bp);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_HAVE_HW_BREAKPOINT */
|
||||
|
||||
/* Move contents to the DABR register */
|
||||
task->thread.dabr = data;
|
||||
|
|
|
@ -20,6 +20,7 @@ obj-$(CONFIG_PPC64) += copypage_64.o copyuser_64.o \
|
|||
memcpy_64.o usercopy_64.o mem_64.o string.o
|
||||
obj-$(CONFIG_XMON) += sstep.o ldstfp.o
|
||||
obj-$(CONFIG_KPROBES) += sstep.o ldstfp.o
|
||||
obj-$(CONFIG_HAVE_HW_BREAKPOINT) += sstep.o ldstfp.o
|
||||
|
||||
ifeq ($(CONFIG_PPC64),y)
|
||||
obj-$(CONFIG_SMP) += locks.o
|
||||
|
|
Loading…
Reference in New Issue