clk: tegra: Fix xusb_hs_src clock hierarchy
Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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@ -233,6 +233,7 @@ enum clk_id {
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tegra_clk_xusb_hs_src,
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tegra_clk_xusb_ss,
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tegra_clk_xusb_ss_src,
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tegra_clk_xusb_ss_div2,
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tegra_clk_max,
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};
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@ -340,6 +340,11 @@ static u32 mux_clkm_pllre_clk32_480M_pllc_ref_idx[] = {
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[0] = 0, [1] = 1, [2] = 3, [3] = 3, [4] = 4, [5] = 7,
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};
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static const char *mux_ss_60M[] = {
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"xusb_ss_div2", "pll_u_60M"
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};
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#define mux_ss_60M_idx NULL
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static const char *mux_d_audio_clk[] = {
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"pll_a_out0", "pll_p", "clk_m", "spdif_in_sync", "i2s0_sync",
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"i2s1_sync", "i2s2_sync", "i2s3_sync", "i2s4_sync", "vimclk_sync",
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@ -501,6 +506,7 @@ static struct tegra_periph_init_data periph_clks[] = {
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XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_falcon_src),
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XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_fs_src),
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XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_ss_src),
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NODIV("xusb_hs_src", mux_ss_60M, CLK_SOURCE_XUSB_SS_SRC, 25, MASK(1), 143, TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_hs_src, NULL),
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XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA_PERIPH_NO_RESET, tegra_clk_xusb_dev_src),
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};
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@ -142,7 +142,6 @@
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#define UTMIPLL_HW_PWRDN_CFG0_IDDQ_SWCTL BIT(0)
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#define CLK_SOURCE_CSITE 0x1d4
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#define CLK_SOURCE_XUSB_SS_SRC 0x610
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#define CLK_SOURCE_EMC 0x19c
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/* PLLM override registers */
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@ -834,6 +833,7 @@ static struct tegra_clk tegra114_clks[tegra_clk_max] __initdata = {
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[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA114_CLK_XUSB_FALCON_SRC, .present = true },
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[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA114_CLK_XUSB_FS_SRC, .present = true },
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[tegra_clk_xusb_ss_src] = { .dt_id = TEGRA114_CLK_XUSB_SS_SRC, .present = true },
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[tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA114_CLK_XUSB_SS_DIV2, .present = true},
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[tegra_clk_xusb_dev_src] = { .dt_id = TEGRA114_CLK_XUSB_DEV_SRC, .present = true },
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[tegra_clk_xusb_dev] = { .dt_id = TEGRA114_CLK_XUSB_DEV, .present = true },
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[tegra_clk_xusb_hs_src] = { .dt_id = TEGRA114_CLK_XUSB_HS_SRC, .present = true },
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@ -1182,16 +1182,11 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base,
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void __iomem *pmc_base)
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{
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struct clk *clk;
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u32 val;
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/* xusb_hs_src */
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val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
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val |= BIT(25); /* always select PLLU_60M */
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writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
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clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
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1, 1);
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clks[TEGRA114_CLK_XUSB_HS_SRC] = clk;
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/* xusb_ss_div2 */
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clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
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1, 2);
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clks[TEGRA114_CLK_XUSB_SS_DIV2] = clk;
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/* dsia mux */
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clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
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@ -30,7 +30,6 @@
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#define CLK_SOURCE_CSITE 0x1d4
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#define CLK_SOURCE_EMC 0x19c
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#define CLK_SOURCE_XUSB_SS_SRC 0x610
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#define PLLC_BASE 0x80
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#define PLLC_OUT 0x84
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@ -925,6 +924,7 @@ static struct tegra_clk tegra124_clks[tegra_clk_max] __initdata = {
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[tegra_clk_xusb_falcon_src] = { .dt_id = TEGRA124_CLK_XUSB_FALCON_SRC, .present = true },
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[tegra_clk_xusb_fs_src] = { .dt_id = TEGRA124_CLK_XUSB_FS_SRC, .present = true },
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[tegra_clk_xusb_ss_src] = { .dt_id = TEGRA124_CLK_XUSB_SS_SRC, .present = true },
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[tegra_clk_xusb_ss_div2] = { .dt_id = TEGRA124_CLK_XUSB_SS_DIV2, .present = true },
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[tegra_clk_xusb_dev_src] = { .dt_id = TEGRA124_CLK_XUSB_DEV_SRC, .present = true },
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[tegra_clk_xusb_dev] = { .dt_id = TEGRA124_CLK_XUSB_DEV, .present = true },
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[tegra_clk_xusb_hs_src] = { .dt_id = TEGRA124_CLK_XUSB_HS_SRC, .present = true },
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@ -1105,16 +1105,11 @@ static __init void tegra124_periph_clk_init(void __iomem *clk_base,
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void __iomem *pmc_base)
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{
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struct clk *clk;
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u32 val;
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/* xusb_hs_src */
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val = readl(clk_base + CLK_SOURCE_XUSB_SS_SRC);
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val |= BIT(25); /* always select PLLU_60M */
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writel(val, clk_base + CLK_SOURCE_XUSB_SS_SRC);
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clk = clk_register_fixed_factor(NULL, "xusb_hs_src", "pll_u_60M", 0,
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1, 1);
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clks[TEGRA124_CLK_XUSB_HS_SRC] = clk;
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/* xusb_ss_div2 */
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clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
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1, 2);
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clks[TEGRA124_CLK_XUSB_SS_DIV2] = clk;
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/* dsia mux */
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clk = clk_register_mux(NULL, "dsia_mux", mux_plld_out0_plld2_out0,
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@ -337,6 +337,7 @@
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#define TEGRA114_CLK_CLK_OUT_3_MUX 308
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#define TEGRA114_CLK_DSIA_MUX 309
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#define TEGRA114_CLK_DSIB_MUX 310
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#define TEGRA114_CLK_CLK_MAX 311
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#define TEGRA114_CLK_XUSB_SS_DIV2 311
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#define TEGRA114_CLK_CLK_MAX 312
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#endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
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@ -336,6 +336,7 @@
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#define TEGRA124_CLK_DSIA_MUX 309
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#define TEGRA124_CLK_DSIB_MUX 310
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#define TEGRA124_CLK_SOR0_LVDS 311
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#define TEGRA124_CLK_CLK_MAX 312
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#define TEGRA124_CLK_XUSB_SS_DIV2 312
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#define TEGRA124_CLK_CLK_MAX 313
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#endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_H */
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