KVM: PPC: Book3S HV: Set server for passed-through interrupts
When a guest has a PCI pass-through device with an interrupt, it will direct the interrupt to a particular guest VCPU. In fact the physical interrupt might arrive on any CPU, and then get delivered to the target VCPU in the emulated XICS (guest interrupt controller), and eventually delivered to the target VCPU. Now that we have code to handle device interrupts in real mode without exiting to the host kernel, there is an advantage to having the device interrupt arrive on the same sub(core) as the target VCPU is running on. In this situation, the interrupt can be delivered to the target VCPU without any exit to the host kernel (using a hypervisor doorbell interrupt between threads if necessary). This patch aims to get passed-through device interrupts arriving on the correct core by setting the interrupt server in the real hardware XICS for the interrupt to the first thread in the (sub)core where its target VCPU is running. We do this in the real-mode H_EOI code because the H_EOI handler already needs to look at the emulated ICS state for the interrupt (whereas the H_XIRR handler doesn't), and we know we are running in the target VCPU context at that point. We set the server CPU in hardware using an OPAL call, regardless of what the IRQ affinity mask for the interrupt says, and without updating the affinity mask. This amounts to saying that when an interrupt is passed through to a guest, as a matter of policy we allow the guest's affinity for the interrupt to override the host's. This is inspired by an earlier patch from Suresh Warrier, although none of this code came from that earlier patch. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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@ -479,6 +479,10 @@ extern int kvmppc_xics_set_icp(struct kvm_vcpu *vcpu, u64 icpval);
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extern int kvmppc_xics_connect_vcpu(struct kvm_device *dev,
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extern int kvmppc_xics_connect_vcpu(struct kvm_device *dev,
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struct kvm_vcpu *vcpu, u32 cpu);
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struct kvm_vcpu *vcpu, u32 cpu);
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extern void kvmppc_xics_ipi_action(void);
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extern void kvmppc_xics_ipi_action(void);
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extern void kvmppc_xics_set_mapped(struct kvm *kvm, unsigned long guest_irq,
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unsigned long host_irq);
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extern void kvmppc_xics_clr_mapped(struct kvm *kvm, unsigned long guest_irq,
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unsigned long host_irq);
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extern long kvmppc_deliver_irq_passthru(struct kvm_vcpu *vcpu, u32 xirr,
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extern long kvmppc_deliver_irq_passthru(struct kvm_vcpu *vcpu, u32 xirr,
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struct kvmppc_irq_map *irq_map,
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struct kvmppc_irq_map *irq_map,
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struct kvmppc_passthru_irqmap *pimap);
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struct kvmppc_passthru_irqmap *pimap);
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@ -67,6 +67,7 @@ int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
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int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
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int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
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uint64_t offset, uint32_t data);
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uint64_t offset, uint32_t data);
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int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
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int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
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int64_t opal_rm_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
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int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
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int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
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int64_t opal_register_exception_handler(uint64_t opal_exception,
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int64_t opal_register_exception_handler(uint64_t opal_exception,
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uint64_t handler_address,
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uint64_t handler_address,
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@ -3515,6 +3515,8 @@ static int kvmppc_set_passthru_irq(struct kvm *kvm, int host_irq, int guest_gsi)
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if (i == pimap->n_mapped)
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if (i == pimap->n_mapped)
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pimap->n_mapped++;
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pimap->n_mapped++;
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kvmppc_xics_set_mapped(kvm, guest_gsi, desc->irq_data.hwirq);
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mutex_unlock(&kvm->lock);
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mutex_unlock(&kvm->lock);
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return 0;
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return 0;
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@ -3551,6 +3553,8 @@ static int kvmppc_clr_passthru_irq(struct kvm *kvm, int host_irq, int guest_gsi)
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return -ENODEV;
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return -ENODEV;
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}
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}
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kvmppc_xics_clr_mapped(kvm, guest_gsi, pimap->mapped[i].r_hwirq);
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/* invalidate the entry */
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/* invalidate the entry */
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pimap->mapped[i].r_hwirq = 0;
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pimap->mapped[i].r_hwirq = 0;
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@ -22,6 +22,7 @@
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#include <asm/pgtable.h>
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#include <asm/pgtable.h>
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#include <asm/ppc-opcode.h>
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#include <asm/ppc-opcode.h>
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#include <asm/pnv-pci.h>
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#include <asm/pnv-pci.h>
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#include <asm/opal.h>
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#include "book3s_xics.h"
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#include "book3s_xics.h"
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@ -34,6 +35,7 @@ EXPORT_SYMBOL(kvm_irq_bypass);
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static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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static void icp_rm_deliver_irq(struct kvmppc_xics *xics, struct kvmppc_icp *icp,
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u32 new_irq);
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u32 new_irq);
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static int xics_opal_rm_set_server(unsigned int hw_irq, int server_cpu);
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/* -- ICS routines -- */
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/* -- ICS routines -- */
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static void ics_rm_check_resend(struct kvmppc_xics *xics,
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static void ics_rm_check_resend(struct kvmppc_xics *xics,
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@ -713,6 +715,13 @@ int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
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icp->rm_action |= XICS_RM_NOTIFY_EOI;
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icp->rm_action |= XICS_RM_NOTIFY_EOI;
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icp->rm_eoied_irq = irq;
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icp->rm_eoied_irq = irq;
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}
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}
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if (state->host_irq && state->intr_cpu != -1) {
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int pcpu = cpu_first_thread_sibling(raw_smp_processor_id());
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if (state->intr_cpu != pcpu)
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xics_opal_rm_set_server(state->host_irq, pcpu);
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state->intr_cpu = -1;
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}
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bail:
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bail:
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return check_too_hard(xics, icp);
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return check_too_hard(xics, icp);
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}
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}
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@ -736,6 +745,13 @@ static void icp_eoi(struct irq_chip *c, u32 hwirq, u32 xirr)
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_stwcix(xics_phys + XICS_XIRR, xirr);
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_stwcix(xics_phys + XICS_XIRR, xirr);
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}
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}
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static int xics_opal_rm_set_server(unsigned int hw_irq, int server_cpu)
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{
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unsigned int mangle_cpu = get_hard_smp_processor_id(server_cpu) << 2;
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return opal_rm_set_xive(hw_irq, mangle_cpu, DEFAULT_PRIORITY);
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}
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/*
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/*
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* Increment a per-CPU 32-bit unsigned integer variable.
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* Increment a per-CPU 32-bit unsigned integer variable.
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* Safe to call in real-mode. Handles vmalloc'ed addresses
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* Safe to call in real-mode. Handles vmalloc'ed addresses
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@ -99,6 +99,10 @@ static int ics_deliver_irq(struct kvmppc_xics *xics, u32 irq, u32 level)
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return 0;
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return 0;
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}
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}
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/* Record which CPU this arrived on for passed-through interrupts */
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if (state->host_irq)
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state->intr_cpu = raw_smp_processor_id();
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/* Attempt delivery */
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/* Attempt delivery */
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icp_deliver_irq(xics, NULL, irq);
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icp_deliver_irq(xics, NULL, irq);
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@ -1438,3 +1442,34 @@ int kvm_irq_map_chip_pin(struct kvm *kvm, unsigned irqchip, unsigned pin)
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{
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{
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return pin;
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return pin;
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}
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}
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void kvmppc_xics_set_mapped(struct kvm *kvm, unsigned long irq,
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unsigned long host_irq)
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{
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struct kvmppc_xics *xics = kvm->arch.xics;
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struct kvmppc_ics *ics;
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u16 idx;
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ics = kvmppc_xics_find_ics(xics, irq, &idx);
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if (!ics)
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return;
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ics->irq_state[idx].host_irq = host_irq;
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ics->irq_state[idx].intr_cpu = -1;
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}
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EXPORT_SYMBOL_GPL(kvmppc_xics_set_mapped);
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void kvmppc_xics_clr_mapped(struct kvm *kvm, unsigned long irq,
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unsigned long host_irq)
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{
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struct kvmppc_xics *xics = kvm->arch.xics;
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struct kvmppc_ics *ics;
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u16 idx;
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ics = kvmppc_xics_find_ics(xics, irq, &idx);
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if (!ics)
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return;
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ics->irq_state[idx].host_irq = 0;
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}
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EXPORT_SYMBOL_GPL(kvmppc_xics_clr_mapped);
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@ -42,6 +42,8 @@ struct ics_irq_state {
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u8 lsi; /* level-sensitive interrupt */
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u8 lsi; /* level-sensitive interrupt */
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u8 asserted; /* Only for LSI */
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u8 asserted; /* Only for LSI */
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u8 exists;
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u8 exists;
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int intr_cpu;
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u32 host_irq;
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};
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};
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/* Atomic ICP state, updated with a single compare & swap */
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/* Atomic ICP state, updated with a single compare & swap */
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@ -208,6 +208,7 @@ OPAL_CALL(opal_pci_config_write_byte, OPAL_PCI_CONFIG_WRITE_BYTE);
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OPAL_CALL(opal_pci_config_write_half_word, OPAL_PCI_CONFIG_WRITE_HALF_WORD);
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OPAL_CALL(opal_pci_config_write_half_word, OPAL_PCI_CONFIG_WRITE_HALF_WORD);
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OPAL_CALL(opal_pci_config_write_word, OPAL_PCI_CONFIG_WRITE_WORD);
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OPAL_CALL(opal_pci_config_write_word, OPAL_PCI_CONFIG_WRITE_WORD);
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OPAL_CALL(opal_set_xive, OPAL_SET_XIVE);
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OPAL_CALL(opal_set_xive, OPAL_SET_XIVE);
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OPAL_CALL_REAL(opal_rm_set_xive, OPAL_SET_XIVE);
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OPAL_CALL(opal_get_xive, OPAL_GET_XIVE);
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OPAL_CALL(opal_get_xive, OPAL_GET_XIVE);
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OPAL_CALL(opal_register_exception_handler, OPAL_REGISTER_OPAL_EXCEPTION_HANDLER);
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OPAL_CALL(opal_register_exception_handler, OPAL_REGISTER_OPAL_EXCEPTION_HANDLER);
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OPAL_CALL(opal_pci_eeh_freeze_status, OPAL_PCI_EEH_FREEZE_STATUS);
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OPAL_CALL(opal_pci_eeh_freeze_status, OPAL_PCI_EEH_FREEZE_STATUS);
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