mvebu dt64 for 4.18 (part 1)
- Allow using Armada 3700 gpio controller as interrupt one too - Describe SPI flash on the EspressoBin - Mark ahci as dma-coherent for Armada 7K/8K - Add 10G interface support Armada 7K/8K based boards (including MacBin) -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQYqXDMF3cvSLY+g9cLBhiOFHI71QUCWv8DYwAKCRALBhiOFHI7 1XpdAKCGSSJQjUSkwu7luezYH9Hz0rRkkQCgoPNedba4WxKrKck5aIFiqHyaFBk= =pUZZ -----END PGP SIGNATURE----- Merge tag 'mvebu-dt64-4.18-1' of git://git.infradead.org/linux-mvebu into next/dt mvebu dt64 for 4.18 (part 1) - Allow using Armada 3700 gpio controller as interrupt one too - Describe SPI flash on the EspressoBin - Mark ahci as dma-coherent for Armada 7K/8K - Add 10G interface support Armada 7K/8K based boards (including MacBin) * tag 'mvebu-dt64-4.18-1' of git://git.infradead.org/linux-mvebu: arm64: dts: marvell: armada-37xx: mark the gpio controllers as irq controller arm64: dts: marvell: 7040-db: describe the 10G interface as fixed-link arm64: dts: marvell: 8040-db: describe the 10G interfaces as fixed-link arm64: dts: marvell: mcbin: enable the fourth network interface arm64: dts: marvell: mcbin: add 10G SFP support arm64: dts: marvell: mark CP110 ahci as dma-coherent arm64: dts: armada-3720-espressobin: wire up spi flash Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
5d91dcfafc
@ -63,6 +63,33 @@
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status = "okay";
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};
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&spi0 {
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status = "okay";
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flash@0 {
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reg = <0>;
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compatible = "winbond,w25q32dw", "jedec,spi-flash";
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spi-max-frequency = <104000000>;
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m25p,fast-read;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "uboot";
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reg = <0 0x180000>;
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};
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partition@180000 {
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label = "ubootenv";
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reg = <0x180000 0x10000>;
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};
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};
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};
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};
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/* Exported on the micro USB connector J5 through an FTDI */
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&uart0 {
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pinctrl-names = "default";
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@ -148,10 +148,13 @@
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compatible = "marvell,armada3710-nb-pinctrl",
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"syscon", "simple-mfd";
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reg = <0x13800 0x100>, <0x13C00 0x20>;
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/* MPP1[19:0] */
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gpionb: gpio {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_nb 0 0 36>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts =
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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@ -209,10 +212,13 @@
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compatible = "marvell,armada3710-sb-pinctrl",
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"syscon", "simple-mfd";
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reg = <0x18800 0x100>, <0x18C00 0x20>;
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/* MPP2[23:0] */
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gpiosb: gpio {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_sb 0 0 30>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts =
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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@ -242,6 +242,11 @@
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phy-mode = "10gbase-kr";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp0_comphy2 0>;
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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&cp0_eth1 {
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@ -177,6 +177,11 @@
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&cp0_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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&cp0_eth2 {
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@ -303,6 +308,11 @@
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&cp1_eth0 {
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status = "okay";
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phy-mode = "10gbase-kr";
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fixed-link {
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speed = <10000>;
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full-duplex;
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};
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};
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&cp1_eth1 {
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@ -27,6 +27,7 @@
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ethernet0 = &cp0_eth0;
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ethernet1 = &cp1_eth0;
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ethernet2 = &cp1_eth1;
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ethernet3 = &cp1_eth2;
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};
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/* Regulator labels correspond with schematics */
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@ -64,6 +65,42 @@
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compatible = "usb-nop-xceiv";
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vcc-supply = <&v_5v0_usb3_hst_vbus>;
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};
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sfp_eth0: sfp-eth0 {
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/* CON15,16 - CPM lane 4 */
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compatible = "sff,sfp";
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i2c-bus = <&sfpp0_i2c>;
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los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_sfpp0_pins>;
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};
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sfp_eth1: sfp-eth1 {
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/* CON17,18 - CPS lane 4 */
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compatible = "sff,sfp";
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i2c-bus = <&sfpp1_i2c>;
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los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>;
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};
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sfp_eth3: sfp-eth3 {
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/* CON3,4 - CPS lane 5 */
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compatible = "sff,sfp";
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i2c-bus = <&sfp_1g_i2c>;
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los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>;
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tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>;
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};
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};
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&uart0 {
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@ -171,6 +208,10 @@
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marvell,pins = "mpp47";
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marvell,function = "gpio";
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};
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cp0_sfp_1g_pins: sfp-1g-pins {
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marvell,pins = "mpp51", "mpp53", "mpp54";
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marvell,function = "gpio";
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};
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cp0_pcie_pins: pcie-pins {
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marvell,pins = "mpp52";
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marvell,function = "gpio";
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@ -180,6 +221,10 @@
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"mpp60", "mpp61";
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marvell,function = "sdio";
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};
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cp0_sfpp1_pins: sfpp1-pins {
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marvell,pins = "mpp62";
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marvell,function = "gpio";
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};
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};
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&cp0_xmdio {
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@ -188,11 +233,13 @@
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phy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0>;
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sfp = <&sfp_eth0>;
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};
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phy8: ethernet-phy@8 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <8>;
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sfp = <&sfp_eth1>;
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};
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};
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@ -257,7 +304,22 @@
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phys = <&cp1_comphy0 1>;
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};
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&cp1_eth2 {
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/* CPS Lane 5 */
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status = "okay";
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/* Network PHY */
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phy-mode = "2500base-x";
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managed = "in-band-status";
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/* Generic PHY, providing serdes lanes */
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phys = <&cp1_comphy5 2>;
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sfp = <&sfp_eth3>;
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};
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&cp1_pinctrl {
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cp1_sfpp1_pins: sfpp1-pins {
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marvell,pins = "mpp8", "mpp10", "mpp11";
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marvell,function = "gpio";
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};
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cp1_spi1_pins: spi1-pins {
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marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
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marvell,function = "spi1";
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@ -266,6 +328,14 @@
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marvell,pins = "mpp6", "mpp7";
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marvell,function = "uart0";
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};
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cp1_sfp_1g_pins: sfp-1g-pins {
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marvell,pins = "mpp24";
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marvell,function = "gpio";
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};
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cp1_sfpp0_pins: sfpp0-pins {
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marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29";
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marvell,function = "gpio";
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};
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};
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/* J27 UART header */
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@ -233,6 +233,7 @@
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compatible = "marvell,armada-8k-ahci",
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"generic-ahci";
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reg = <0x540000 0x30000>;
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dma-coherent;
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interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CP110_LABEL(clk) 1 15>,
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<&CP110_LABEL(clk) 1 16>;
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