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Merge tag 'tegra-for-3.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc 

From Stephen Warren:
ARM: tegra: core SoC code enhancements

Various small clock initialization table and driver changes to support
WiFi modules, SPI controllers, and host1x (graphics/display hardware).

Various AHB/APB-related clocks were added to the Tegra30 clock driver.

The level 2 cache initialization is now driven by data from device tree,
and the cache configuration tweaked.

AUXDATA is added to support SPI controllers and host1x.

Code to decode Tegra's "speedo" process identification fuses is added.

This pull request is based on tegra-for-3.8-cleanup.

* tag 'tegra-for-3.8-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (26 commits)
  ARM: tegra: Add Tegra30 host1x clock support
  ARM: tegra: Add AUXDATA for Tegra30 host1x
  ARM: tegra: Add Tegra20 host1x clock support
  ARM: tegra: Add AUXDATA for Tegra20 host1x
  ARM: tegra: Tegra30 speedo-based process identification
  ARM: tegra: Add speedo-based process identification
  ARM: tegra: flexible spare fuse read function
  ARM: tegra: Implement 6395/1 for Tegra
  ARM: tegra: Add OF_DEV_AUXDATA for sflash driver in board dt
  ARM: tegra: enable data prefetch on L2
  ARM: tegra: Add OF_DEV_AUXDATA for SLINK driver in board dt
  ARM: tegra: common: using OF api for L2 cache init
  ARM: tegra: dt: add L2 cache controller
  ARM: tegra30: clocks: add AHB and APB clocks
  ARM: tegra: set up wlan clocks for tegra dt
  ARM: tegra: move irammap.h to mach-tegra
  ARM: tegra: move iomap.h to mach-tegra
  ARM: tegra: remove <mach/dma.h>
  ARM: tegra: move tegra-ahb.h out of arch/arm/mach-tegra/
  ARM: tegra: remove unnecessary includes of <mach/*.h>
  ...
This commit is contained in:
Olof Johansson 2012-11-21 00:21:56 -08:00
parent 5ffd785402 d1d3b978f6
commit 5e505bb9e7
56 changed files with 846 additions and 504 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

63
arch/arm/boot/dts/tegra20-harmony.dts
View File

@ -297,131 +297,98 @@
vinldo9-supply = <&sm2_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
sys_reg: regulator@0 {
reg = <0>;
regulator-compatible = "sys";
sys_reg: sys {
regulator-name = "vdd_sys";
regulator-always-on;
};
regulator@1 {
reg = <1>;
regulator-compatible = "sm0";
sm0 {
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
regulator@2 {
reg = <2>;
regulator-compatible = "sm1";
sm1 {
regulator-name = "vdd_sm1,vdd_cpu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
sm2_reg: regulator@3 {
reg = <3>;
regulator-compatible = "sm2";
sm2_reg: sm2 {
regulator-name = "vdd_sm2,vin_ldo*";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
};
regulator@4 {
reg = <4>;
regulator-compatible = "ldo0";
ldo0 {
regulator-name = "vdd_ldo0,vddio_pex_clk";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@5 {
reg = <5>;
regulator-compatible = "ldo1";
ldo1 {
regulator-name = "vdd_ldo1,avdd_pll*";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
regulator@6 {
reg = <6>;
regulator-compatible = "ldo2";
ldo2 {
regulator-name = "vdd_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
regulator@7 {
reg = <7>;
regulator-compatible = "ldo3";
ldo3 {
regulator-name = "vdd_ldo3,avdd_usb*";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
regulator@8 {
reg = <8>;
regulator-compatible = "ldo4";
ldo4 {
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
regulator@9 {
reg = <9>;
regulator-compatible = "ldo5";
ldo5 {
regulator-name = "vdd_ldo5,vcore_mmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@10 {
reg = <10>;
regulator-compatible = "ldo6";
ldo6 {
regulator-name = "vdd_ldo6,avdd_vdac";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@11 {
reg = <11>;
regulator-compatible = "ldo7";
ldo7 {
regulator-name = "vdd_ldo7,avdd_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@12 {
reg = <12>;
regulator-compatible = "ldo8";
ldo8 {
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@13 {
reg = <13>;
regulator-compatible = "ldo9";
ldo9 {
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@14 {
reg = <14>;
regulator-compatible = "ldo_rtc";
ldo_rtc {
regulator-name = "vdd_rtc_out,vdd_cell";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

59
arch/arm/boot/dts/tegra20-paz00.dts
View File

@ -291,37 +291,26 @@
vinldo9-supply = <&sm2_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
sys_reg: regulator@0 {
reg = <0>;
regulator-compatible = "sys";
sys_reg: sys {
regulator-name = "vdd_sys";
regulator-always-on;
};
regulator@1 {
reg = <1>;
regulator-compatible = "sm0";
sm0 {
regulator-name = "+1.2vs_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
regulator@2 {
reg = <2>;
regulator-compatible = "sm1";
sm1 {
regulator-name = "+1.0vs_sm1,vdd_cpu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
sm2_reg: regulator@3 {
reg = <3>;
regulator-compatible = "sm2";
sm2_reg: sm2 {
regulator-name = "+3.7vs_sm2,vin_ldo*";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
@ -330,53 +319,41 @@
/* LDO0 is not connected to anything */
regulator@5 {
reg = <5>;
regulator-compatible = "ldo1";
ldo1 {
regulator-name = "+1.1vs_ldo1,avdd_pll*";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
regulator@6 {
reg = <6>;
regulator-compatible = "ldo2";
ldo2 {
regulator-name = "+1.2vs_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
regulator@7 {
reg = <7>;
regulator-compatible = "ldo3";
ldo3 {
regulator-name = "+3.3vs_ldo3,avdd_usb*";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
regulator@8 {
reg = <8>;
regulator-compatible = "ldo4";
ldo4 {
regulator-name = "+1.8vs_ldo4,avdd_osc,vddio_sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
regulator@9 {
reg = <9>;
regulator-compatible = "ldo5";
ldo5 {
regulator-name = "+2.85vs_ldo5,vcore_mmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@10 {
reg = <10>;
regulator-compatible = "ldo6";
ldo6 {
/*
* Research indicates this should be
* 1.8v; other boards that use this
@ -390,34 +367,26 @@
regulator-max-microvolt = <1800000>;
};
regulator@11 {
reg = <11>;
regulator-compatible = "ldo7";
ldo7 {
regulator-name = "+3.3vs_ldo7,avdd_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@12 {
reg = <12>;
regulator-compatible = "ldo8";
ldo8 {
regulator-name = "+1.8vs_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@13 {
reg = <13>;
regulator-compatible = "ldo9";
ldo9 {
regulator-name = "+2.85vs_ldo9,vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@14 {
reg = <14>;
regulator-compatible = "ldo_rtc";
ldo_rtc {
regulator-name = "+3.3vs_rtc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

59
arch/arm/boot/dts/tegra20-seaboard.dts
View File

@ -395,37 +395,26 @@
vinldo9-supply = <&sm2_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
sys_reg: regulator@0 {
reg = <0>;
regulator-compatible = "sys";
sys_reg: sys {
regulator-name = "vdd_sys";
regulator-always-on;
};
regulator@1 {
reg = <1>;
regulator-compatible = "sm0";
sm0 {
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
};
regulator@2 {
reg = <2>;
regulator-compatible = "sm1";
sm1 {
regulator-name = "vdd_sm1,vdd_cpu";
regulator-min-microvolt = <1125000>;
regulator-max-microvolt = <1125000>;
regulator-always-on;
};
sm2_reg: regulator@3 {
reg = <3>;
regulator-compatible = "sm2";
sm2_reg: sm2 {
regulator-name = "vdd_sm2,vin_ldo*";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
@ -434,86 +423,66 @@
/* LDO0 is not connected to anything */
regulator@5 {
reg = <5>;
regulator-compatible = "ldo1";
ldo1 {
regulator-name = "vdd_ldo1,avdd_pll*";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
regulator@6 {
reg = <6>;
regulator-compatible = "ldo2";
ldo2 {
regulator-name = "vdd_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
regulator@7 {
reg = <7>;
regulator-compatible = "ldo3";
ldo3 {
regulator-name = "vdd_ldo3,avdd_usb*";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
regulator@8 {
reg = <8>;
regulator-compatible = "ldo4";
ldo4 {
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
regulator@9 {
reg = <9>;
regulator-compatible = "ldo5";
ldo5 {
regulator-name = "vdd_ldo5,vcore_mmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@10 {
reg = <10>;
regulator-compatible = "ldo6";
ldo6 {
regulator-name = "vdd_ldo6,avdd_vdac,vddio_vi,vddio_cam";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@11 {
reg = <11>;
regulator-compatible = "ldo7";
ldo7 {
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@12 {
reg = <12>;
regulator-compatible = "ldo8";
ldo8 {
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@13 {
reg = <13>;
regulator-compatible = "ldo9";
ldo9 {
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@14 {
reg = <14>;
regulator-compatible = "ldo_rtc";
ldo_rtc {
regulator-name = "vdd_rtc_out,vdd_cell";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

63
arch/arm/boot/dts/tegra20-tamonten.dtsi
View File

@ -271,97 +271,72 @@
vinldo9-supply = <&sm2_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
sys_reg: regulator@0 {
reg = <0>;
regulator-compatible = "sys";
sys_reg: sys {
regulator-name = "vdd_sys";
regulator-always-on;
};
regulator@1 {
reg = <1>;
regulator-compatible = "sm0";
sm0 {
regulator-name = "vdd_sys_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
regulator@2 {
reg = <2>;
regulator-compatible = "sm1";
sm1 {
regulator-name = "vdd_sys_sm1,vdd_cpu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
sm2_reg: regulator@3 {
reg = <3>;
regulator-compatible = "sm2";
sm2_reg: sm2 {
regulator-name = "vdd_sys_sm2,vin_ldo*";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
};
regulator@4 {
reg = <4>;
regulator-compatible = "ldo0";
ldo0 {
regulator-name = "vdd_ldo0,vddio_pex_clk";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@5 {
reg = <5>;
regulator-compatible = "ldo1";
ldo1 {
regulator-name = "vdd_ldo1,avdd_pll*";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
regulator@6 {
reg = <6>;
regulator-compatible = "ldo2";
ldo2 {
regulator-name = "vdd_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
regulator@7 {
reg = <7>;
regulator-compatible = "ldo3";
ldo3 {
regulator-name = "vdd_ldo3,avdd_usb*";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
regulator@8 {
reg = <8>;
regulator-compatible = "ldo4";
ldo4 {
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
regulator@9 {
reg = <9>;
regulator-compatible = "ldo5";
ldo5 {
regulator-name = "vdd_ldo5,vcore_mmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
regulator@10 {
reg = <10>;
regulator-compatible = "ldo6";
ldo6 {
regulator-name = "vdd_ldo6,avdd_vdac";
/*
* According to the Tegra 2 Automotive
@ -373,25 +348,19 @@
regulator-max-microvolt = <2850000>;
};
regulator@11 {
reg = <11>;
regulator-compatible = "ldo7";
ldo7 {
regulator-name = "vdd_ldo7,avdd_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@12 {
reg = <12>;
regulator-compatible = "ldo8";
ldo8 {
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@13 {
reg = <13>;
regulator-compatible = "ldo9";
ldo9 {
regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
/*
* According to the Tegra 2 Automotive
@ -404,9 +373,7 @@
regulator-always-on;
};
regulator@14 {
reg = <14>;
regulator-compatible = "ldo_rtc";
ldo_rtc {
regulator-name = "vdd_rtc_out";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

59
arch/arm/boot/dts/tegra20-ventana.dts
View File

@ -311,37 +311,26 @@
vinldo9-supply = <&sm2_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
sys_reg: regulator@0 {
reg = <0>;
regulator-compatible = "sys";
sys_reg: sys {
regulator-name = "vdd_sys";
regulator-always-on;
};
regulator@1 {
reg = <1>;
regulator-compatible = "sm0";
sm0 {
regulator-name = "vdd_sm0,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
regulator@2 {
reg = <2>;
regulator-compatible = "sm1";
sm1 {
regulator-name = "vdd_sm1,vdd_cpu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
sm2_reg: regulator@3 {
reg = <3>;
regulator-compatible = "sm2";
sm2_reg: sm2 {
regulator-name = "vdd_sm2,vin_ldo*";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
@ -350,86 +339,66 @@
/* LDO0 is not connected to anything */
regulator@5 {
reg = <5>;
regulator-compatible = "ldo1";
ldo1 {
regulator-name = "vdd_ldo1,avdd_pll*";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
regulator@6 {
reg = <6>;
regulator-compatible = "ldo2";
ldo2 {
regulator-name = "vdd_ldo2,vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
regulator@7 {
reg = <7>;
regulator-compatible = "ldo3";
ldo3 {
regulator-name = "vdd_ldo3,avdd_usb*";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
regulator@8 {
reg = <8>;
regulator-compatible = "ldo4";
ldo4 {
regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
regulator@9 {
reg = <9>;
regulator-compatible = "ldo5";
ldo5 {
regulator-name = "vdd_ldo5,vcore_mmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@10 {
reg = <10>;
regulator-compatible = "ldo6";
ldo6 {
regulator-name = "vdd_ldo6,avdd_vdac";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@11 {
reg = <11>;
regulator-compatible = "ldo7";
ldo7 {
regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@12 {
reg = <12>;
regulator-compatible = "ldo8";
ldo8 {
regulator-name = "vdd_ldo8,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@13 {
reg = <13>;
regulator-compatible = "ldo9";
ldo9 {
regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
regulator-always-on;
};
regulator@14 {
reg = <14>;
regulator-compatible = "ldo_rtc";
ldo_rtc {
regulator-name = "vdd_rtc_out,vdd_cell";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

119
arch/arm/boot/dts/tegra20-whistler.dts
View File

@ -295,243 +295,182 @@
in20-supply = <&mbatt_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
mbatt_reg: regulator@0 {
reg = <0>;
regulator-compatible = "mbatt";
mbatt_reg: mbatt {
regulator-name = "vbat_pmu";
regulator-always-on;
};
regulator@1 {
reg = <1>;
regulator-compatible = "sd1";
sd1 {
regulator-name = "nvvdd_sv1,vdd_cpu_pmu";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
regulator@2 {
reg = <2>;
regulator-compatible = "sd2";
sd2 {
regulator-name = "nvvdd_sv2,vdd_core";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
nvvdd_sv3_reg: regulator@3 {
reg = <3>;
regulator-compatible = "sd3";
nvvdd_sv3_reg: sd3 {
regulator-name = "nvvdd_sv3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
regulator@4 {
reg = <4>;
regulator-compatible = "ldo1";
ldo1 {
regulator-name = "nvvdd_ldo1,vddio_rx_ddr,vcore_acc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
regulator@5 {
reg = <5>;
regulator-compatible = "ldo2";
ldo2 {
regulator-name = "nvvdd_ldo2,avdd_pll*";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
regulator@6 {
reg = <6>;
regulator-compatible = "ldo3";
ldo3 {
regulator-name = "nvvdd_ldo3,vcom_1v8b";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
regulator@7 {
reg = <7>;
regulator-compatible = "ldo4";
ldo4 {
regulator-name = "nvvdd_ldo4,avdd_usb*";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
regulator@8 {
reg = <8>;
regulator-compatible = "ldo5";
ldo5 {
regulator-name = "nvvdd_ldo5,vcore_mmc,avdd_lcd1,vddio_1wire";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
regulator@9 {
reg = <9>;
regulator-compatible = "ldo6";
ldo6 {
regulator-name = "nvvdd_ldo6,avdd_hdmi_pll";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@10 {
reg = <10>;
regulator-compatible = "ldo7";
ldo7 {
regulator-name = "nvvdd_ldo7,avddio_audio";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
regulator@11 {
reg = <11>;
regulator-compatible = "ldo8";
ldo8 {
regulator-name = "nvvdd_ldo8,vcom_3v0,vcore_cmps";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
regulator@12 {
reg = <12>;
regulator-compatible = "ldo9";
ldo9 {
regulator-name = "nvvdd_ldo9,avdd_cam*";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
regulator@13 {
reg = <13>;
regulator-compatible = "ldo10";
ldo10 {
regulator-name = "nvvdd_ldo10,avdd_usb_ic_3v0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
regulator@14 {
reg = <14>;
regulator-compatible = "ldo11";
ldo11 {
regulator-name = "nvvdd_ldo11,vddio_pex_clk,vcom_33,avdd_hdmi";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@15 {
reg = <15>;
regulator-compatible = "ldo12";
ldo12 {
regulator-name = "nvvdd_ldo12,vddio_sdio";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
};
regulator@16 {
reg = <16>;
regulator-compatible = "ldo13";
ldo13 {
regulator-name = "nvvdd_ldo13,vcore_phtn,vdd_af";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
regulator@17 {
reg = <17>;
regulator-compatible = "ldo14";
ldo14 {
regulator-name = "nvvdd_ldo14,avdd_vdac";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
regulator@18 {
reg = <18>;
regulator-compatible = "ldo15";
ldo15 {
regulator-name = "nvvdd_ldo15,vcore_temp,vddio_hdcp";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
regulator@19 {
reg = <19>;
regulator-compatible = "ldo16";
ldo16 {
regulator-name = "nvvdd_ldo16,vdd_dbrtr";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1300000>;
};
regulator@20 {
reg = <20>;
regulator-compatible = "ldo17";
ldo17 {
regulator-name = "nvvdd_ldo17,vddio_mipi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
regulator@21 {
reg = <21>;
regulator-compatible = "ldo18";
ldo18 {
regulator-name = "nvvdd_ldo18,vddio_vi,vcore_cam*";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
regulator@22 {
reg = <22>;
regulator-compatible = "ldo19";
ldo19 {
regulator-name = "nvvdd_ldo19,avdd_lcd2,vddio_lx";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
regulator@23 {
reg = <23>;
regulator-compatible = "ldo20";
ldo20 {
regulator-name = "nvvdd_ldo20,vddio_ddr_1v2,vddio_hsic,vcom_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
regulator@24 {
reg = <24>;
regulator-compatible = "out5v";
out5v {
regulator-name = "usb0_vbus_reg";
};
regulator@25 {
reg = <25>;
regulator-compatible = "out33v";
out33v {
regulator-name = "pmu_out3v3";
};
regulator@26 {
reg = <26>;
regulator-compatible = "bbat";
bbat {
regulator-name = "pmu_bbat";
regulator-min-microvolt = <2400000>;
regulator-max-microvolt = <2400000>;
regulator-always-on;
};
regulator@27 {
reg = <27>;
regulator-compatible = "sdby";
sdby {
regulator-name = "vdd_aon";
regulator-always-on;
};
regulator@28 {
reg = <28>;
regulator-compatible = "vrtc";
vrtc {
regulator-name = "vrtc,pmu_vccadc";
regulator-always-on;
};

9
arch/arm/boot/dts/tegra20.dtsi
View File

@ -4,6 +4,15 @@
compatible = "nvidia,tegra20";
interrupt-parent = <&intc>;
cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <5 5 2>;
arm,tag-latency = <4 4 2>;
cache-unified;
cache-level = <2>;
};
intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000

47
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@ -171,56 +171,41 @@
vccio-supply = <&vdd_ac_bat_reg>;
regulators {
#address-cells = <1>;
#size-cells = <0>;
vdd1_reg: regulator@0 {
reg = <0>;
regulator-compatible = "vdd1";
vdd1_reg: vdd1 {
regulator-name = "vddio_ddr_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vdd2_reg: regulator@1 {
reg = <1>;
regulator-compatible = "vdd2";
vdd2_reg: vdd2 {
regulator-name = "vdd_1v5_gen";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
};
vddctrl_reg: regulator@2 {
reg = <2>;
regulator-compatible = "vddctrl";
vddctrl_reg: vddctrl {
regulator-name = "vdd_cpu,vdd_sys";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
};
vio_reg: regulator@3 {
reg = <3>;
regulator-compatible = "vio";
vio_reg: vio {
regulator-name = "vdd_1v8_gen";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
ldo1_reg: regulator@4 {
reg = <4>;
regulator-compatible = "ldo1";
ldo1_reg: ldo1 {
regulator-name = "vdd_pexa,vdd_pexb";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
ldo2_reg: regulator@5 {
reg = <5>;
regulator-compatible = "ldo2";
ldo2_reg: ldo2 {
regulator-name = "vdd_sata,avdd_plle";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
@ -228,44 +213,34 @@
/* LDO3 is not connected to anything */
ldo4_reg: regulator@7 {
reg = <7>;
regulator-compatible = "ldo4";
ldo4_reg: ldo4 {
regulator-name = "vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
ldo5_reg: regulator@8 {
reg = <8>;
regulator-compatible = "ldo5";
ldo5_reg: ldo5 {
regulator-name = "vddio_sdmmc,avdd_vdac";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo6_reg: regulator@9 {
reg = <9>;
regulator-compatible = "ldo6";
ldo6_reg: ldo6 {
regulator-name = "avdd_dsi_csi,pwrdet_mipi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo7_reg: regulator@10 {
reg = <10>;
regulator-compatible = "ldo7";
ldo7_reg: ldo7 {
regulator-name = "vdd_pllm,x,u,a_p_c_s";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
ldo8_reg: regulator@11 {
reg = <11>;
regulator-compatible = "ldo8";
ldo8_reg: ldo8 {
regulator-name = "vdd_ddr_hs";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;

9
arch/arm/boot/dts/tegra30.dtsi
View File

@ -4,6 +4,15 @@
compatible = "nvidia,tegra30";
interrupt-parent = <&intc>;
cache-controller@50043000 {
compatible = "arm,pl310-cache";
reg = <0x50043000 0x1000>;
arm,data-latency = <6 6 2>;
arm,tag-latency = <5 5 2>;
cache-unified;
cache-level = <2>;
};
intc: interrupt-controller {
compatible = "arm,cortex-a9-gic";
reg = <0x50041000 0x1000

2
arch/arm/mach-tegra/Makefile
View File

@ -12,10 +12,12 @@ obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CPU_IDLE) += sleep.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t20.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_SMP) += reset.o

5
arch/arm/mach-tegra/apbio.c
View File

@ -15,7 +15,6 @@
#include <linux/kernel.h>
#include <linux/io.h>
#include <mach/iomap.h>
#include <linux/of.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
@ -24,9 +23,8 @@
#include <linux/sched.h>
#include <linux/mutex.h>
#include <mach/dma.h>
#include "apbio.h"
#include "iomap.h"
#if defined(CONFIG_TEGRA20_APB_DMA)
static DEFINE_MUTEX(tegra_apb_dma_lock);
@ -71,7 +69,6 @@ bool tegra_apb_dma_init(void)
dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dma_sconfig.slave_id = TEGRA_DMA_REQ_SEL_CNTR;
dma_sconfig.src_maxburst = 1;
dma_sconfig.dst_maxburst = 1;

27
arch/arm/mach-tegra/board-dt-tegra20.c
View File

@ -40,12 +40,10 @@
#include <asm/mach/time.h>
#include <asm/setup.h>
#include <mach/iomap.h>
#include <mach/irqs.h>
#include "board.h"
#include "clock.h"
#include "common.h"
#include "iomap.h"
struct tegra_ehci_platform_data tegra_ehci1_pdata = {
.operating_mode = TEGRA_USB_OTG,
@ -91,6 +89,17 @@ struct of_dev_auxdata tegra20_auxdata_lookup[] __initdata = {
&tegra_ehci3_pdata),
OF_DEV_AUXDATA("nvidia,tegra20-apbdma", TEGRA_APB_DMA_BASE, "tegra-apbdma", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-sflash", 0x7000c380, "spi", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D400, "spi_tegra.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D600, "spi_tegra.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000D800, "spi_tegra.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-slink", 0x7000DA00, "spi_tegra.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-host1x", 0x50000000, "host1x", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54200000, "tegradc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-dc", 0x54240000, "tegradc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-hdmi", 0x54280000, "hdmi", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-dsi", 0x54300000, "dsi", NULL),
OF_DEV_AUXDATA("nvidia,tegra20-tvo", 0x542c0000, "tvo", NULL),
{}
};
@ -104,8 +113,20 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
{ "pll_a", "pll_p_out1", 56448000, true },
{ "pll_a_out0", "pll_a", 11289600, true },
{ "cdev1", NULL, 0, true },
{ "blink", "clk_32k", 32768, true },
{ "i2s1", "pll_a_out0", 11289600, false},
{ "i2s2", "pll_a_out0", 11289600, false},
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
{ "spi", "pll_p", 20000000, false },
{ "sbc1", "pll_p", 100000000, false },
{ "sbc2", "pll_p", 100000000, false },
{ "sbc3", "pll_p", 100000000, false },
{ "sbc4", "pll_p", 100000000, false },
{ "host1x", "pll_c", 150000000, false },
{ "disp1", "pll_p", 600000000, false },
{ "disp2", "pll_p", 600000000, false },
{ NULL, NULL, 0, 0},
};

28
arch/arm/mach-tegra/board-dt-tegra30.c
View File

@ -33,11 +33,10 @@
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <mach/iomap.h>
#include "board.h"
#include "clock.h"
#include "common.h"
#include "iomap.h"
struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra20-sdhci", 0x78000000, "sdhci-tegra.0", NULL),
@ -52,6 +51,18 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-apbdma", 0x6000a000, "tegra-apbdma", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-pwm", TEGRA_PWFM_BASE, "tegra-pwm", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D400, "spi_tegra.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D600, "spi_tegra.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000D800, "spi_tegra.2", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DA00, "spi_tegra.3", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DC00, "spi_tegra.4", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-slink", 0x7000DE00, "spi_tegra.5", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-host1x", 0x50000000, "host1x", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54200000, "tegradc.0", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-dc", 0x54240000, "tegradc.1", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-hdmi", 0x54280000, "hdmi", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-dsi", 0x54300000, "dsi", NULL),
OF_DEV_AUXDATA("nvidia,tegra30-tvo", 0x542c0000, "tvo", NULL),
{}
};
@ -62,11 +73,24 @@ static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
{ "pll_a_out0", "pll_a", 11289600, true },
{ "extern1", "pll_a_out0", 0, true },
{ "clk_out_1", "extern1", 0, true },
{ "blink", "clk_32k", 32768, true },
{ "i2s0", "pll_a_out0", 11289600, false},
{ "i2s1", "pll_a_out0", 11289600, false},
{ "i2s2", "pll_a_out0", 11289600, false},
{ "i2s3", "pll_a_out0", 11289600, false},
{ "i2s4", "pll_a_out0", 11289600, false},
{ "sdmmc1", "pll_p", 48000000, false},
{ "sdmmc3", "pll_p", 48000000, false},
{ "sdmmc4", "pll_p", 48000000, false},
{ "sbc1", "pll_p", 100000000, false},
{ "sbc2", "pll_p", 100000000, false},
{ "sbc3", "pll_p", 100000000, false},
{ "sbc4", "pll_p", 100000000, false},
{ "sbc5", "pll_p", 100000000, false},
{ "sbc6", "pll_p", 100000000, false},
{ "host1x", "pll_c", 150000000, false},
{ "disp1", "pll_p", 600000000, false},
{ "disp2", "pll_p", 600000000, false},
{ NULL, NULL, 0, 0},
};

2
arch/arm/mach-tegra/clock.c
View File

@ -27,8 +27,6 @@
#include <linux/seq_file.h>
#include <linux/slab.h>
#include <mach/clk.h>
#include "board.h"
#include "clock.h"
#include "tegra_cpu_car.h"

19
arch/arm/mach-tegra/common.c
View File

@ -26,13 +26,13 @@
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
#include <mach/iomap.h>
#include <mach/powergate.h>
#include "board.h"
#include "clock.h"
#include "common.h"
#include "fuse.h"
#include "iomap.h"
#include "pmc.h"
#include "apbio.h"
#include "sleep.h"
@ -104,25 +104,26 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {
{ "clk_m", NULL, 0, true },
{ "pll_p", "clk_m", 408000000, true },
{ "pll_p_out1", "pll_p", 9600000, true },
{ "pll_p_out4", "pll_p", 102000000, true },
{ "sclk", "pll_p_out4", 102000000, true },
{ "hclk", "sclk", 102000000, true },
{ "pclk", "hclk", 51000000, true },
{ NULL, NULL, 0, 0},
};
#endif
static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)
static void __init tegra_init_cache(void)
{
#ifdef CONFIG_CACHE_L2X0
void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
u32 aux_ctrl, cache_type;
writel_relaxed(tag_latency, p + L2X0_TAG_LATENCY_CTRL);
writel_relaxed(data_latency, p + L2X0_DATA_LATENCY_CTRL);
cache_type = readl(p + L2X0_CACHE_TYPE);
aux_ctrl = (cache_type & 0x700) << (17-8);
aux_ctrl |= 0x6C000001;
aux_ctrl |= 0x7C400001;
l2x0_init(p, aux_ctrl, 0x8200c3fe);
l2x0_of_init(aux_ctrl, 0x8200c3fe);
#endif
}
@ -134,7 +135,7 @@ void __init tegra20_init_early(void)
tegra_init_fuse();
tegra2_init_clocks();
tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache(0x331, 0x441);
tegra_init_cache();
tegra_pmc_init();
tegra_powergate_init();
tegra20_hotplug_init();
@ -147,7 +148,7 @@ void __init tegra30_init_early(void)
tegra_init_fuse();
tegra30_init_clocks();
tegra_clk_init_from_table(tegra30_clk_init_table);
tegra_init_cache(0x441, 0x551);
tegra_init_cache();
tegra_pmc_init();
tegra_powergate_init();
tegra30_hotplug_init();

3
arch/arm/mach-tegra/cpu-tegra.c
View File

@ -30,9 +30,6 @@
#include <linux/io.h>
#include <linux/suspend.h>
#include <mach/clk.h>
/* Frequency table index must be sequential starting at 0 */
static struct cpufreq_frequency_table freq_table[] = {
{ 0, 216000 },

2
arch/arm/mach-tegra/cpuidle.c
View File

@ -29,8 +29,6 @@
#include <asm/proc-fns.h>
#include <mach/iomap.h>
static int tegra_idle_enter_lp3(struct cpuidle_device *dev,
struct cpuidle_driver *drv, int index);

3
arch/arm/mach-tegra/flowctrl.c
View File

@ -22,9 +22,8 @@
#include <linux/kernel.h>
#include <linux/io.h>
#include <mach/iomap.h>
#include "flowctrl.h"
#include "iomap.h"
u8 flowctrl_offset_halt_cpu[] = {
FLOW_CTRL_HALT_CPU0_EVENTS,

52
arch/arm/mach-tegra/fuse.c
View File

@ -21,22 +21,28 @@
#include <linux/io.h>
#include <linux/export.h>
#include <mach/iomap.h>
#include "fuse.h"
#include "iomap.h"
#include "apbio.h"
#define FUSE_UID_LOW 0x108
#define FUSE_UID_HIGH 0x10c
#define FUSE_SKU_INFO 0x110
#define FUSE_SPARE_BIT 0x200
#define TEGRA20_FUSE_SPARE_BIT 0x200
#define TEGRA30_FUSE_SPARE_BIT 0x244
int tegra_sku_id;
int tegra_cpu_process_id;
int tegra_core_process_id;
int tegra_chip_id;
int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
int tegra_soc_speedo_id;
enum tegra_revision tegra_revision;
static int tegra_fuse_spare_bit;
static void (*tegra_init_speedo_data)(void);
/* The BCT to use at boot is specified by board straps that can be read
* through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs.
*/
@ -57,14 +63,14 @@ static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
[TEGRA_REVISION_A04] = "A04",
};
static inline u32 tegra_fuse_readl(unsigned long offset)
u32 tegra_fuse_readl(unsigned long offset)
{
return tegra_apb_readl(TEGRA_FUSE_BASE + offset);
}
static inline bool get_spare_fuse(int bit)
bool tegra_spare_fuse(int bit)
{
return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
return tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4);
}
static enum tegra_revision tegra_get_revision(u32 id)
@ -78,7 +84,7 @@ static enum tegra_revision tegra_get_revision(u32 id)
return TEGRA_REVISION_A02;
case 3:
if (tegra_chip_id == TEGRA20 &&
(get_spare_fuse(18) || get_spare_fuse(19)))
(tegra_spare_fuse(18) || tegra_spare_fuse(19)))
return TEGRA_REVISION_A03p;
else
return TEGRA_REVISION_A03;
@ -89,6 +95,16 @@ static enum tegra_revision tegra_get_revision(u32 id)
}
}
static void tegra_get_process_id(void)
{
u32 reg;
reg = tegra_fuse_readl(tegra_fuse_spare_bit);
tegra_cpu_process_id = (reg >> 6) & 3;
reg = tegra_fuse_readl(tegra_fuse_spare_bit);
tegra_core_process_id = (reg >> 12) & 3;
}
void tegra_init_fuse(void)
{
u32 id;
@ -100,19 +116,29 @@ void tegra_init_fuse(void)
reg = tegra_fuse_readl(FUSE_SKU_INFO);
tegra_sku_id = reg & 0xFF;
reg = tegra_fuse_readl(FUSE_SPARE_BIT);
tegra_cpu_process_id = (reg >> 6) & 3;
reg = tegra_fuse_readl(FUSE_SPARE_BIT);
tegra_core_process_id = (reg >> 12) & 3;
reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
tegra_chip_id = (id >> 8) & 0xff;
switch (tegra_chip_id) {
case TEGRA20:
tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
tegra_init_speedo_data = &tegra20_init_speedo_data;
break;
case TEGRA30:
tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
tegra_init_speedo_data = &tegra30_init_speedo_data;
break;
default:
pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
tegra_init_speedo_data = &tegra_get_process_id;
}
tegra_revision = tegra_get_revision(id);
tegra_init_speedo_data();
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
tegra_revision_name[tegra_revision],

16
arch/arm/mach-tegra/fuse.h
View File

@ -42,11 +42,27 @@ extern int tegra_sku_id;
extern int tegra_cpu_process_id;
extern int tegra_core_process_id;
extern int tegra_chip_id;
extern int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
extern int tegra_soc_speedo_id;
extern enum tegra_revision tegra_revision;
extern int tegra_bct_strapping;
unsigned long long tegra_chip_uid(void);
void tegra_init_fuse(void);
bool tegra_spare_fuse(int bit);
u32 tegra_fuse_readl(unsigned long offset);
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
void tegra20_init_speedo_data(void);
#else
static inline void tegra20_init_speedo_data(void) {}
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
void tegra30_init_speedo_data(void);
#else
static inline void tegra30_init_speedo_data(void) {}
#endif
#endif

3
arch/arm/mach-tegra/headsmp.S
View File

@ -3,9 +3,8 @@
#include <asm/cache.h>
#include <mach/iomap.h>
#include "flowctrl.h"
#include "iomap.h"
#include "reset.h"
#include "sleep.h"

4
arch/arm/mach-tegra/include/mach/debug-macro.S
View File

@ -26,8 +26,8 @@
#include <linux/serial_reg.h>
#include <mach/iomap.h>
#include <mach/irammap.h>
#include "../../iomap.h"
#include "../../irammap.h"
.macro addruart, rp, rv, tmp
adr \rp, 99f @ actual addr of 99f

54
arch/arm/mach-tegra/include/mach/dma.h
View File

@ -1,54 +0,0 @@
/*
* arch/arm/mach-tegra/include/mach/dma.h
*
* Copyright (c) 2008-2009, NVIDIA Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#ifndef __MACH_TEGRA_DMA_H
#define __MACH_TEGRA_DMA_H
#include <linux/list.h>
#define TEGRA_DMA_REQ_SEL_CNTR 0
#define TEGRA_DMA_REQ_SEL_I2S_2 1
#define TEGRA_DMA_REQ_SEL_I2S_1 2
#define TEGRA_DMA_REQ_SEL_SPD_I 3
#define TEGRA_DMA_REQ_SEL_UI_I 4
#define TEGRA_DMA_REQ_SEL_MIPI 5
#define TEGRA_DMA_REQ_SEL_I2S2_2 6
#define TEGRA_DMA_REQ_SEL_I2S2_1 7
#define TEGRA_DMA_REQ_SEL_UARTA 8
#define TEGRA_DMA_REQ_SEL_UARTB 9
#define TEGRA_DMA_REQ_SEL_UARTC 10
#define TEGRA_DMA_REQ_SEL_SPI 11
#define TEGRA_DMA_REQ_SEL_AC97 12
#define TEGRA_DMA_REQ_SEL_ACMODEM 13
#define TEGRA_DMA_REQ_SEL_SL4B 14
#define TEGRA_DMA_REQ_SEL_SL2B1 15
#define TEGRA_DMA_REQ_SEL_SL2B2 16
#define TEGRA_DMA_REQ_SEL_SL2B3 17
#define TEGRA_DMA_REQ_SEL_SL2B4 18
#define TEGRA_DMA_REQ_SEL_UARTD 19
#define TEGRA_DMA_REQ_SEL_UARTE 20
#define TEGRA_DMA_REQ_SEL_I2C 21
#define TEGRA_DMA_REQ_SEL_I2C2 22
#define TEGRA_DMA_REQ_SEL_I2C3 23
#define TEGRA_DMA_REQ_SEL_DVC_I2C 24
#define TEGRA_DMA_REQ_SEL_OWR 25
#define TEGRA_DMA_REQ_SEL_INVALID 31
#endif

2
arch/arm/mach-tegra/include/mach/powergate.h
View File

@ -20,6 +20,8 @@
#ifndef _MACH_TEGRA_POWERGATE_H_
#define _MACH_TEGRA_POWERGATE_H_
struct clk;
#define TEGRA_POWERGATE_CPU 0
#define TEGRA_POWERGATE_3D 1
#define TEGRA_POWERGATE_VENC 2

4
arch/arm/mach-tegra/include/mach/uncompress.h
View File

@ -28,8 +28,8 @@
#include <linux/types.h>
#include <linux/serial_reg.h>
#include <mach/iomap.h>
#include <mach/irammap.h>
#include "../../iomap.h"
#include "../../irammap.h"
#define BIT(x) (1 << (x))
#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))

2
arch/arm/mach-tegra/io.c
View File

@ -26,9 +26,9 @@
#include <asm/page.h>
#include <asm/mach/map.h>
#include <mach/iomap.h>
#include "board.h"
#include "iomap.h"
static struct map_desc tegra_io_desc[] __initdata = {
{

2
arch/arm/mach-tegra/include/mach/iomap.h → arch/arm/mach-tegra/iomap.h
View File

@ -1,6 +1,4 @@
/*
* arch/arm/mach-tegra/include/mach/iomap.h
*
* Copyright (C) 2010 Google, Inc.
*
* Author:

0
arch/arm/mach-tegra/include/mach/irammap.h → arch/arm/mach-tegra/irammap.h
View File

3
arch/arm/mach-tegra/irq.c
View File

@ -25,9 +25,8 @@
#include <asm/hardware/gic.h>
#include <mach/iomap.h>
#include "board.h"
#include "iomap.h"
#define ICTLR_CPU_IEP_VFIQ 0x08
#define ICTLR_CPU_IEP_FIR 0x14

2
arch/arm/mach-tegra/pcie.c
View File

@ -37,11 +37,11 @@
#include <asm/sizes.h>
#include <asm/mach/pci.h>
#include <mach/iomap.h>
#include <mach/clk.h>
#include <mach/powergate.h>
#include "board.h"
#include "iomap.h"
/* register definitions */
#define AFI_OFFSET 0x3800

3
arch/arm/mach-tegra/platsmp.c
View File

@ -24,8 +24,6 @@
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
#include <mach/clk.h>
#include <mach/iomap.h>
#include <mach/powergate.h>
#include "fuse.h"
@ -34,6 +32,7 @@
#include "tegra_cpu_car.h"
#include "common.h"
#include "iomap.h"
extern void tegra_secondary_startup(void);

2
arch/arm/mach-tegra/pmc.c
View File

@ -19,7 +19,7 @@
#include <linux/io.h>
#include <linux/of.h>
#include <mach/iomap.h>
#include "iomap.h"
#define PMC_CTRL 0x0
#define PMC_CTRL_INTR_LOW (1 << 17)

2
arch/arm/mach-tegra/powergate.c
View File

@ -28,10 +28,10 @@
#include <linux/spinlock.h>
#include <mach/clk.h>
#include <mach/iomap.h>
#include <mach/powergate.h>
#include "fuse.h"
#include "iomap.h"
#define PWRGATE_TOGGLE 0x30
#define PWRGATE_TOGGLE_START (1 << 8)

5
arch/arm/mach-tegra/reset.c
View File

@ -22,9 +22,8 @@
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/iomap.h>
#include <mach/irammap.h>
#include "iomap.h"
#include "irammap.h"
#include "reset.h"
#include "fuse.h"

2
arch/arm/mach-tegra/sleep-t20.S
View File

@ -22,8 +22,6 @@
#include <asm/assembler.h>
#include <mach/iomap.h>
#include "sleep.h"
#include "flowctrl.h"

2
arch/arm/mach-tegra/sleep-t30.S
View File

@ -18,8 +18,6 @@
#include <asm/assembler.h>
#include <mach/iomap.h>
#include "sleep.h"
#include "flowctrl.h"

2
arch/arm/mach-tegra/sleep.S
View File

@ -26,7 +26,7 @@
#include <asm/assembler.h>
#include <mach/iomap.h>
#include "iomap.h"
#include "flowctrl.h"
#include "sleep.h"

2
arch/arm/mach-tegra/sleep.h
View File

@ -17,7 +17,7 @@
#ifndef __MACH_TEGRA_SLEEP_H
#define __MACH_TEGRA_SLEEP_H
#include <mach/iomap.h>
#include "iomap.h"
#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
+ IO_CPU_VIRT)

3
arch/arm/mach-tegra/tegra20_clocks.c
View File

@ -27,10 +27,9 @@
#include <linux/clkdev.h>
#include <linux/clk.h>
#include <mach/iomap.h>
#include "clock.h"
#include "fuse.h"
#include "iomap.h"
#include "tegra2_emc.h"
#include "tegra_cpu_car.h"

13
arch/arm/mach-tegra/tegra20_clocks_data.c
View File

@ -27,8 +27,6 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <mach/iomap.h>
#include "clock.h"
#include "fuse.h"
#include "tegra2_emc.h"
@ -248,11 +246,16 @@ static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
{ 19200000, 216000000, 135, 12, 1, 3},
{ 26000000, 216000000, 216, 26, 1, 4},
{ 12000000, 297000000, 99, 4, 1, 4 },
{ 12000000, 339000000, 113, 4, 1, 4 },
{ 12000000, 594000000, 594, 12, 1, 8},
{ 13000000, 594000000, 594, 13, 1, 8},
{ 19200000, 594000000, 495, 16, 1, 8},
{ 26000000, 594000000, 594, 26, 1, 8},
{ 12000000, 616000000, 616, 12, 1, 8},
{ 12000000, 1000000000, 1000, 12, 1, 12},
{ 13000000, 1000000000, 1000, 13, 1, 12},
{ 19200000, 1000000000, 625, 12, 1, 8},
@ -1038,9 +1041,6 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
CLK_DUPLICATE("usbd", "utmip-pad", NULL),
CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
CLK_DUPLICATE("usbd", "tegra-otg", NULL),
CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
@ -1053,6 +1053,9 @@ static struct clk_duplicate tegra_clk_duplicates[] = {
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.1", "fast-clk"),
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
CLK_DUPLICATE("pll_d_out0", "hdmi", "parent"),
};
#define CLK(dev, con, ck) \

109
arch/arm/mach-tegra/tegra20_speedo.c Normal file
View File

@ -0,0 +1,109 @@
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
#include <linux/bug.h>
#include "fuse.h"
#define CPU_SPEEDO_LSBIT 20
#define CPU_SPEEDO_MSBIT 29
#define CPU_SPEEDO_REDUND_LSBIT 30
#define CPU_SPEEDO_REDUND_MSBIT 39
#define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT)
#define CORE_SPEEDO_LSBIT 40
#define CORE_SPEEDO_MSBIT 47
#define CORE_SPEEDO_REDUND_LSBIT 48
#define CORE_SPEEDO_REDUND_MSBIT 55
#define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT)
#define SPEEDO_MULT 4
#define PROCESS_CORNERS_NUM 4
#define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2)
#define SPEEDO_ID_SELECT_1(sku) \
(((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \
((sku) != 27) && ((sku) != 28))
enum {
SPEEDO_ID_0,
SPEEDO_ID_1,
SPEEDO_ID_2,
SPEEDO_ID_COUNT,
};
static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = {
{315, 366, 420, UINT_MAX},
{303, 368, 419, UINT_MAX},
{316, 331, 383, UINT_MAX},
};
static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = {
{165, 195, 224, UINT_MAX},
{165, 195, 224, UINT_MAX},
{165, 195, 224, UINT_MAX},
};
void tegra20_init_speedo_data(void)
{
u32 reg;
u32 val;
int i;
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT);
if (SPEEDO_ID_SELECT_0(tegra_revision))
tegra_soc_speedo_id = SPEEDO_ID_0;
else if (SPEEDO_ID_SELECT_1(tegra_sku_id))
tegra_soc_speedo_id = SPEEDO_ID_1;
else
tegra_soc_speedo_id = SPEEDO_ID_2;
val = 0;
for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) {
reg = tegra_spare_fuse(i) |
tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS);
val = (val << 1) | (reg & 0x1);
}
val = val * SPEEDO_MULT;
pr_debug("%s CPU speedo value %u\n", __func__, val);
for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
if (val <= cpu_process_speedos[tegra_soc_speedo_id][i])
break;
}
tegra_cpu_process_id = i;
val = 0;
for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) {
reg = tegra_spare_fuse(i) |
tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS);
val = (val << 1) | (reg & 0x1);
}
val = val * SPEEDO_MULT;
pr_debug("%s Core speedo value %u\n", __func__, val);
for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) {
if (val <= core_process_speedos[tegra_soc_speedo_id][i])
break;
}
tegra_core_process_id = i;
pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id);
}

2
arch/arm/mach-tegra/tegra2_emc.c
View File

@ -25,8 +25,6 @@
#include <linux/platform_device.h>
#include <linux/platform_data/tegra_emc.h>
#include <mach/iomap.h>
#include "tegra2_emc.h"
#include "fuse.h"

109
arch/arm/mach-tegra/tegra30_clocks.c
View File

@ -31,10 +31,9 @@
#include <asm/clkdev.h>
#include <mach/iomap.h>
#include "clock.h"
#include "fuse.h"
#include "iomap.h"
#include "tegra_cpu_car.h"
#define USE_PLL_LOCK_BITS 0
@ -792,6 +791,112 @@ struct clk_ops tegra30_twd_ops = {
.recalc_rate = tegra30_twd_clk_recalc_rate,
};
/* bus clock functions */
static int tegra30_bus_clk_is_enabled(struct clk_hw *hw)
{
struct clk_tegra *c = to_clk_tegra(hw);
u32 val = clk_readl(c->reg);
c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
return c->state;
}
static int tegra30_bus_clk_enable(struct clk_hw *hw)
{
struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
val = clk_readl(c->reg);
val &= ~(BUS_CLK_DISABLE << c->reg_shift);
clk_writel(val, c->reg);
return 0;
}
static void tegra30_bus_clk_disable(struct clk_hw *hw)
{
struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
val = clk_readl(c->reg);
val |= BUS_CLK_DISABLE << c->reg_shift;
clk_writel(val, c->reg);
}
static unsigned long tegra30_bus_clk_recalc_rate(struct clk_hw *hw,
unsigned long prate)
{
struct clk_tegra *c = to_clk_tegra(hw);
u32 val = clk_readl(c->reg);
u64 rate = prate;
c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
c->mul = 1;
if (c->mul != 0 && c->div != 0) {
rate *= c->mul;
rate += c->div - 1; /* round up */
do_div(rate, c->div);
}
return rate;
}
static int tegra30_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_tegra *c = to_clk_tegra(hw);
int ret = -EINVAL;
u32 val;
int i;
val = clk_readl(c->reg);
for (i = 1; i <= 4; i++) {
if (rate == parent_rate / i) {
val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
val |= (i - 1) << c->reg_shift;
clk_writel(val, c->reg);
c->div = i;
c->mul = 1;
ret = 0;
break;
}
}
return ret;
}
static long tegra30_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
unsigned long parent_rate = *prate;
s64 divider;
if (rate >= parent_rate)
return parent_rate;
divider = parent_rate;
divider += rate - 1;
do_div(divider, rate);
if (divider < 0)
return divider;
if (divider > 4)
divider = 4;
do_div(parent_rate, divider);
return parent_rate;
}
struct clk_ops tegra30_bus_ops = {
.is_enabled = tegra30_bus_clk_is_enabled,
.enable = tegra30_bus_clk_enable,
.disable = tegra30_bus_clk_disable,
.set_rate = tegra30_bus_clk_set_rate,
.round_rate = tegra30_bus_clk_round_rate,
.recalc_rate = tegra30_bus_clk_recalc_rate,
};
/* Blink output functions */
static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
{

1
arch/arm/mach-tegra/tegra30_clocks.h
View File

@ -34,6 +34,7 @@ extern struct clk_ops tegra_clk_out_ops;
extern struct clk_ops tegra30_super_ops;
extern struct clk_ops tegra30_blink_clk_ops;
extern struct clk_ops tegra30_twd_ops;
extern struct clk_ops tegra30_bus_ops;
extern struct clk_ops tegra30_periph_clk_ops;
extern struct clk_ops tegra30_dsib_clk_ops;
extern struct clk_ops tegra_nand_clk_ops;

51
arch/arm/mach-tegra/tegra30_clocks_data.c
View File

@ -711,6 +711,50 @@ static struct clk tegra_clk_sclk = {
.num_parents = ARRAY_SIZE(mux_sclk),
};
static const char *tegra_hclk_parent_names[] = {
"tegra_sclk",
};
static struct clk *tegra_hclk_parents[] = {
&tegra_clk_sclk,
};
static struct clk tegra_hclk;
static struct clk_tegra tegra_hclk_hw = {
.hw = {
.clk = &tegra_hclk,
},
.flags = DIV_BUS,
.reg = 0x30,
.reg_shift = 4,
.max_rate = 378000000,
.min_rate = 12000000,
};
DEFINE_CLK_TEGRA(hclk, 0, &tegra30_bus_ops, 0, tegra_hclk_parent_names,
tegra_hclk_parents, &tegra_clk_sclk);
static const char *tegra_pclk_parent_names[] = {
"tegra_hclk",
};
static struct clk *tegra_pclk_parents[] = {
&tegra_hclk,
};
static struct clk tegra_pclk;
static struct clk_tegra tegra_pclk_hw = {
.hw = {
.clk = &tegra_pclk,
},
.flags = DIV_BUS,
.reg = 0x30,
.reg_shift = 0,
.max_rate = 167000000,
.min_rate = 12000000,
};
DEFINE_CLK_TEGRA(pclk, 0, &tegra30_bus_ops, 0, tegra_pclk_parent_names,
tegra_pclk_parents, &tegra_hclk);
static const char *mux_blink[] = {
"clk_32k",
};
@ -1254,8 +1298,6 @@ struct clk_duplicate tegra_clk_duplicates[] = {
CLK_DUPLICATE("usbd", "utmip-pad", NULL),
CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
CLK_DUPLICATE("usbd", "tegra-otg", NULL),
CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
@ -1293,6 +1335,9 @@ struct clk_duplicate tegra_clk_duplicates[] = {
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.2", "fast-clk"),
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.3", "fast-clk"),
CLK_DUPLICATE("pll_p_out3", "tegra-i2c.4", "fast-clk"),
CLK_DUPLICATE("pll_p", "tegradc.0", "parent"),
CLK_DUPLICATE("pll_p", "tegradc.1", "parent"),
CLK_DUPLICATE("pll_d2_out0", "hdmi", "parent"),
};
struct clk *tegra_ptr_clks[] = {
@ -1325,6 +1370,8 @@ struct clk *tegra_ptr_clks[] = {
&tegra_cml1,
&tegra_pciex,
&tegra_clk_sclk,
&tegra_hclk,
&tegra_pclk,
&tegra_clk_blink,
&tegra30_clk_twd,
};

292
arch/arm/mach-tegra/tegra30_speedo.c Normal file
View File

@ -0,0 +1,292 @@
/*
* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/kernel.h>
#include <linux/bug.h>
#include "fuse.h"
#define CORE_PROCESS_CORNERS_NUM 1
#define CPU_PROCESS_CORNERS_NUM 6
#define FUSE_SPEEDO_CALIB_0 0x114
#define FUSE_PACKAGE_INFO 0X1FC
#define FUSE_TEST_PROG_VER 0X128
#define G_SPEEDO_BIT_MINUS1 58
#define G_SPEEDO_BIT_MINUS1_R 59
#define G_SPEEDO_BIT_MINUS2 60
#define G_SPEEDO_BIT_MINUS2_R 61
#define LP_SPEEDO_BIT_MINUS1 62
#define LP_SPEEDO_BIT_MINUS1_R 63
#define LP_SPEEDO_BIT_MINUS2 64
#define LP_SPEEDO_BIT_MINUS2_R 65
enum {
THRESHOLD_INDEX_0,
THRESHOLD_INDEX_1,
THRESHOLD_INDEX_2,
THRESHOLD_INDEX_3,
THRESHOLD_INDEX_4,
THRESHOLD_INDEX_5,
THRESHOLD_INDEX_6,
THRESHOLD_INDEX_7,
THRESHOLD_INDEX_8,
THRESHOLD_INDEX_9,
THRESHOLD_INDEX_10,
THRESHOLD_INDEX_11,
THRESHOLD_INDEX_COUNT,
};
static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
{180},
{170},
{195},
{180},
{168},
{192},
{180},
{170},
{195},
{180},
{180},
{180},
};
static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
{306, 338, 360, 376, UINT_MAX},
{295, 336, 358, 375, UINT_MAX},
{325, 325, 358, 375, UINT_MAX},
{325, 325, 358, 375, UINT_MAX},
{292, 324, 348, 364, UINT_MAX},
{324, 324, 348, 364, UINT_MAX},
{324, 324, 348, 364, UINT_MAX},
{295, 336, 358, 375, UINT_MAX},
{358, 358, 358, 358, 397, UINT_MAX},
{364, 364, 364, 364, 397, UINT_MAX},
{295, 336, 358, 375, 391, UINT_MAX},
{295, 336, 358, 375, 391, UINT_MAX},
};
static int threshold_index;
static int package_id;
static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
{
u32 reg;
int ate_ver;
int bit_minus1;
int bit_minus2;
reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
*speedo_lp = (reg & 0xFFFF) * 4;
*speedo_g = ((reg >> 16) & 0xFFFF) * 4;
ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER);
pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
if (ate_ver >= 26) {
bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1);
bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2);
bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
*speedo_lp |= (bit_minus1 << 1) | bit_minus2;
bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1);
bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2);
bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
*speedo_g |= (bit_minus1 << 1) | bit_minus2;
} else {
*speedo_lp |= 0x3;
*speedo_g |= 0x3;
}
}
static void rev_sku_to_speedo_ids(int rev, int sku)
{
switch (rev) {
case TEGRA_REVISION_A01:
tegra_cpu_speedo_id = 0;
tegra_soc_speedo_id = 0;
threshold_index = THRESHOLD_INDEX_0;
break;
case TEGRA_REVISION_A02:
case TEGRA_REVISION_A03:
switch (sku) {
case 0x87:
case 0x82:
tegra_cpu_speedo_id = 1;
tegra_soc_speedo_id = 1;
threshold_index = THRESHOLD_INDEX_1;
break;
case 0x81:
switch (package_id) {
case 1:
tegra_cpu_speedo_id = 2;
tegra_soc_speedo_id = 2;
threshold_index = THRESHOLD_INDEX_2;
break;
case 2:
tegra_cpu_speedo_id = 4;
tegra_soc_speedo_id = 1;
threshold_index = THRESHOLD_INDEX_7;
break;
default:
pr_err("Tegra30: Unknown pkg %d\n", package_id);
BUG();
break;
}
break;
case 0x80:
switch (package_id) {
case 1:
tegra_cpu_speedo_id = 5;
tegra_soc_speedo_id = 2;
threshold_index = THRESHOLD_INDEX_8;
break;
case 2:
tegra_cpu_speedo_id = 6;
tegra_soc_speedo_id = 2;
threshold_index = THRESHOLD_INDEX_9;
break;
default:
pr_err("Tegra30: Unknown pkg %d\n", package_id);
BUG();
break;
}
break;
case 0x83:
switch (package_id) {
case 1:
tegra_cpu_speedo_id = 7;
tegra_soc_speedo_id = 1;
threshold_index = THRESHOLD_INDEX_10;
break;
case 2:
tegra_cpu_speedo_id = 3;
tegra_soc_speedo_id = 2;
threshold_index = THRESHOLD_INDEX_3;
break;
default:
pr_err("Tegra30: Unknown pkg %d\n", package_id);
BUG();
break;
}
break;
case 0x8F:
tegra_cpu_speedo_id = 8;
tegra_soc_speedo_id = 1;
threshold_index = THRESHOLD_INDEX_11;
break;
case 0x08:
tegra_cpu_speedo_id = 1;
tegra_soc_speedo_id = 1;
threshold_index = THRESHOLD_INDEX_4;
break;
case 0x02:
tegra_cpu_speedo_id = 2;
tegra_soc_speedo_id = 2;
threshold_index = THRESHOLD_INDEX_5;
break;
case 0x04:
tegra_cpu_speedo_id = 3;
tegra_soc_speedo_id = 2;
threshold_index = THRESHOLD_INDEX_6;
break;
case 0:
switch (package_id) {
case 1:
tegra_cpu_speedo_id = 2;
tegra_soc_speedo_id = 2;
threshold_index = THRESHOLD_INDEX_2;
break;
case 2:
tegra_cpu_speedo_id = 3;
tegra_soc_speedo_id = 2;
threshold_index = THRESHOLD_INDEX_3;
break;
default:
pr_err("Tegra30: Unknown pkg %d\n", package_id);
BUG();
break;
}
break;
default:
pr_warn("Tegra30: Unknown SKU %d\n", sku);
tegra_cpu_speedo_id = 0;
tegra_soc_speedo_id = 0;
threshold_index = THRESHOLD_INDEX_0;
break;
}
break;
default:
pr_warn("Tegra30: Unknown chip rev %d\n", rev);
tegra_cpu_speedo_id = 0;
tegra_soc_speedo_id = 0;
threshold_index = THRESHOLD_INDEX_0;
break;
}
}
void tegra30_init_speedo_data(void)
{
u32 cpu_speedo_val;
u32 core_speedo_val;
int i;
BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
THRESHOLD_INDEX_COUNT);
BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
THRESHOLD_INDEX_COUNT);
package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
break;
}
tegra_cpu_process_id = i - 1;
if (tegra_cpu_process_id == -1) {
pr_warn("Tegra30: CPU speedo value %3d out of range",
cpu_speedo_val);
tegra_cpu_process_id = 0;
tegra_cpu_speedo_id = 1;
}
for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
if (core_speedo_val < core_process_speedos[threshold_index][i])
break;
}
tegra_core_process_id = i - 1;
if (tegra_core_process_id == -1) {
pr_warn("Tegra30: CORE speedo value %3d out of range",
core_speedo_val);
tegra_core_process_id = 0;
tegra_soc_speedo_id = 1;
}
pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d",
tegra_cpu_speedo_id, tegra_soc_speedo_id);
}

2
arch/arm/mach-tegra/timer.c
View File

@ -31,11 +31,11 @@
#include <asm/smp_twd.h>
#include <asm/sched_clock.h>
#include <mach/iomap.h>
#include <mach/irqs.h>
#include "board.h"
#include "clock.h"
#include "iomap.h"
#define RTC_SECONDS 0x08
#define RTC_SHADOW_SECONDS 0x0c

1
drivers/amba/tegra-ahb.c
View File

@ -24,6 +24,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/tegra-ahb.h>
#define DRV_NAME "tegra-ahb"

2
drivers/crypto/tegra-aes.c
View File

@ -41,8 +41,6 @@
#include <linux/completion.h>
#include <linux/workqueue.h>
#include <mach/clk.h>
#include <crypto/scatterwalk.h>
#include <crypto/aes.h>
#include <crypto/internal/rng.h>

4
drivers/iommu/tegra-smmu.c
View File

@ -34,13 +34,11 @@
#include <linux/of_iommu.h>
#include <linux/debugfs.h>
#include <linux/seq_file.h>
#include <linux/tegra-ahb.h>
#include <asm/page.h>
#include <asm/cacheflush.h>
#include <mach/iomap.h>
#include <mach/tegra-ahb.h>
enum smmu_hwgrp {
HWGRP_AFI,
HWGRP_AVPC,

1
drivers/staging/nvec/nvec.c
View File

@ -39,7 +39,6 @@
#include <linux/workqueue.h>
#include <mach/clk.h>
#include <mach/iomap.h>
#include "nvec.h"

5
drivers/usb/host/ehci-tegra.c
View File

@ -28,7 +28,10 @@
#include <linux/pm_runtime.h>
#include <linux/usb/tegra_usb_phy.h>
#include <mach/iomap.h>
#define TEGRA_USB_BASE 0xC5000000
#define TEGRA_USB2_BASE 0xC5004000
#define TEGRA_USB3_BASE 0xC5008000
#define TEGRA_USB_DMA_ALIGN 32

4
drivers/usb/phy/tegra_usb_phy.c
View File

@ -29,7 +29,9 @@
#include <linux/usb/ulpi.h>
#include <asm/mach-types.h>
#include <linux/usb/tegra_usb_phy.h>
#include <mach/iomap.h>
#define TEGRA_USB_BASE 0xC5000000
#define TEGRA_USB_SIZE SZ_16K
#define ULPI_VIEWPORT 0x170

6
arch/arm/mach-tegra/include/mach/tegra-ahb.h → include/linux/tegra-ahb.h
View File

@ -11,9 +11,9 @@
* more details.
*/
#ifndef __MACH_TEGRA_AHB_H__
#define __MACH_TEGRA_AHB_H__
#ifndef __LINUX_AHB_H__
#define __LINUX_AHB_H__
extern int tegra_ahb_enable_smmu(struct device_node *ahb);
#endif /* __MACH_TEGRA_AHB_H__ */
#endif /* __LINUX_AHB_H__ */

1
sound/soc/tegra/tegra30_ahub.c
View File

@ -26,7 +26,6 @@
#include <linux/regmap.h>
#include <linux/slab.h>
#include <mach/clk.h>
#include <mach/dma.h>
#include <sound/soc.h>
#include "tegra30_ahub.h"

2
sound/soc/tegra/tegra_pcm.h
View File

@ -31,8 +31,6 @@
#ifndef __TEGRA_PCM_H__
#define __TEGRA_PCM_H__
#include <mach/dma.h>
struct tegra_pcm_dma_params {
unsigned long addr;
unsigned long wrap;