Renesas ARM Based SoC Clock Updates for v3.15
* r7s72100 SoC (RZ/A1H) - Add clock for SH Ethernet - Add RSPI clocks * r8a7791 (R-Car M2) - Add QSPI and SDHI clocks * r8a7790 (R-Car H2) - Add audio clock - Remove legacy DT clocks - Correct SYS DMAC clock defines -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.14 (GNU/Linux) iQIcBAABAgAGBQJTDZ1pAAoJENfPZGlqN0++O98P/R7NOBCLZFI6w7I8eolsuaKQ WMxuqQbX0TUEfnLwN8B23gkEW6008Lfq0c5PTtJRMG7WDyspB1NfrHWxuGbXfe3f u0CBtsRVBleHj7CFyGUKW6d5aoPY04S4+296RF80dDyk95xjlGI7TIX+JCr5yg0u hylB15nw+KKD/UzW6MBmiq+HVqsObkJ2rKyNAWRtzwdAvgO6wOWZHUSR01dF0AaO n1h8GDVmGfahCHhhP1qNrMRyR8qJ6MNVJpGXXTdiyI1S3ON3CpJFvXbjIcg0tfUD crQw1zGR7WTY+7ga7uqdQj3YpvOxexh8YFFvPYZcerOW/bhlrancW4q15OgsNlM2 tl2j59naW1mnqPUTKnfM0yX6qZN0ILL6/yoLmVCvHmO/cJpfajoQ5vuIk9OMiTmx S/zx/BGlCZ6olTiT/7+l6Jn/yctrutS43UhP1qqIPHneX1XM3PHOT3R8TlcrYgOq i2Ugd5QzSKZx3tfpsvu60UlAKYqprs24i/DK0UluJVdgN9Uerx/ArAUR21YIZcBT fJ8pjMJi471CCcstFAVWQETs3iGqPCDFZiwGCrbV/rwPLAO07k/sdf3hZibN8c/g yOa1ezIPcEbLCw4F+O2SVUbnX1cIeS0nPpOcAHaPZsg2hZ8mx70U1k6fO+Z+Assr mlM7KQJ8FMC/ZBNGQAJa =+nyz -----END PGP SIGNATURE----- Merge tag 'renesas-clock-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Merge "Renesas ARM Based SoC Clock Updates for v3.15" from Simon Horman: * r7s72100 SoC (RZ/A1H) - Add clock for SH Ethernet - Add RSPI clocks * r8a7791 (R-Car M2) - Add QSPI and SDHI clocks * r8a7790 (R-Car H2) - Add audio clock - Remove legacy DT clocks - Correct SYS DMAC clock defines * tag 'renesas-clock-for-v3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Remove legacy r8a7790 DT clocks ARM: shmobile: Add r8a7791 legacy SDHI clocks ARM: shmobile: r8a7790: Correct SYS DMAC clock defines ARM: shmobile: r7s72100: Add clock for r7s72100-ether ARM: shmobile: r8a7791 clock: add QSPI clocks ARM: shmobile: r7s72100 clock: Add RSPI clocks for DT ARM: shmobile: r7s72100 clock: Add RSPI clocks ARM: shmobile: r8a7790: add audio clock ARM: shmobile: r8a7778: add audio clock in new style Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
6020dd9b01
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@ -313,6 +313,29 @@
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clock-output-names = "extal";
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};
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/*
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* The external audio clocks are configured as 0 Hz fixed frequency clocks by
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* default. Boards that provide audio clocks should override them.
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*/
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audio_clk_a: audio_clk_a {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "audio_clk_a";
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};
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audio_clk_b: audio_clk_b {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "audio_clk_b";
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};
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audio_clk_c: audio_clk_c {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "audio_clk_c";
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7790-cpg-clocks",
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@ -22,12 +22,15 @@
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#include <mach/common.h>
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#include <mach/r7s72100.h>
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/* registers */
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/* Frequency Control Registers */
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#define FRQCR 0xfcfe0010
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#define FRQCR2 0xfcfe0014
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/* Standby Control Registers */
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#define STBCR3 0xfcfe0420
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#define STBCR4 0xfcfe0424
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#define STBCR7 0xfcfe0430
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#define STBCR9 0xfcfe0438
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#define STBCR10 0xfcfe043c
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#define PLL_RATE 30
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@ -145,15 +148,25 @@ struct clk div4_clks[DIV4_NR] = {
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| CLK_ENABLE_ON_INIT),
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};
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enum { MSTP97, MSTP96, MSTP95, MSTP94,
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enum {
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MSTP107, MSTP106, MSTP105, MSTP104, MSTP103,
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MSTP97, MSTP96, MSTP95, MSTP94,
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MSTP74,
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MSTP47, MSTP46, MSTP45, MSTP44, MSTP43, MSTP42, MSTP41, MSTP40,
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MSTP33, MSTP_NR };
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MSTP33, MSTP_NR
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};
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP107] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 7, 0), /* RSPI0 */
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[MSTP106] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 6, 0), /* RSPI1 */
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[MSTP105] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 5, 0), /* RSPI2 */
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[MSTP104] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 4, 0), /* RSPI3 */
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[MSTP103] = SH_CLK_MSTP8(&peripheral1_clk, STBCR10, 3, 0), /* RSPI4 */
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[MSTP97] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 7, 0), /* RIIC0 */
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[MSTP96] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 6, 0), /* RIIC1 */
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[MSTP95] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 5, 0), /* RIIC2 */
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[MSTP94] = SH_CLK_MSTP8(&peripheral0_clk, STBCR9, 4, 0), /* RIIC3 */
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[MSTP74] = SH_CLK_MSTP8(&peripheral1_clk, STBCR7, 4, 0), /* Ether */
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[MSTP47] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 7, 0), /* SCIF0 */
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[MSTP46] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 6, 0), /* SCIF1 */
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[MSTP45] = SH_CLK_MSTP8(&peripheral1_clk, STBCR4, 5, 0), /* SCIF2 */
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@ -176,10 +189,21 @@ static struct clk_lookup lookups[] = {
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CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
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/* MSTP clocks */
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CLKDEV_DEV_ID("rspi-rz.0", &mstp_clks[MSTP107]),
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CLKDEV_DEV_ID("rspi-rz.1", &mstp_clks[MSTP106]),
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CLKDEV_DEV_ID("rspi-rz.2", &mstp_clks[MSTP105]),
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CLKDEV_DEV_ID("rspi-rz.3", &mstp_clks[MSTP104]),
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CLKDEV_DEV_ID("rspi-rz.4", &mstp_clks[MSTP103]),
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CLKDEV_DEV_ID("e800c800.spi", &mstp_clks[MSTP107]),
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CLKDEV_DEV_ID("e800d000.spi", &mstp_clks[MSTP106]),
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CLKDEV_DEV_ID("e800d800.spi", &mstp_clks[MSTP105]),
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CLKDEV_DEV_ID("e800e000.spi", &mstp_clks[MSTP104]),
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CLKDEV_DEV_ID("e800e800.spi", &mstp_clks[MSTP103]),
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CLKDEV_DEV_ID("fcfee000.i2c", &mstp_clks[MSTP97]),
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CLKDEV_DEV_ID("fcfee400.i2c", &mstp_clks[MSTP96]),
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CLKDEV_DEV_ID("fcfee800.i2c", &mstp_clks[MSTP95]),
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CLKDEV_DEV_ID("fcfeec00.i2c", &mstp_clks[MSTP94]),
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CLKDEV_DEV_ID("r7s72100-ether", &mstp_clks[MSTP74]),
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CLKDEV_CON_ID("mtu2_fck", &mstp_clks[MSTP33]),
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/* ICK */
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@ -221,6 +221,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
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CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
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CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
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CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
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CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
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CLKDEV_ICK_ID("clk_i", "rcar_sound", &s1_clk),
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CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
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CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
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CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
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@ -91,6 +91,15 @@ static struct clk main_clk = {
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.ops = &followparent_clk_ops,
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};
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static struct clk audio_clk_a = {
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};
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static struct clk audio_clk_b = {
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};
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static struct clk audio_clk_c = {
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};
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/*
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* clock ratio of these clock will be updated
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* on r8a7790_clock_init()
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@ -124,6 +133,9 @@ SH_FIXED_RATIO_CLK_SET(ddr_clk, pll3_clk, 1, 8);
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SH_FIXED_RATIO_CLK_SET(mp_clk, pll1_div2_clk, 1, 15);
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static struct clk *main_clks[] = {
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&audio_clk_a,
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&audio_clk_b,
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&audio_clk_c,
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&extal_clk,
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&extal_div2_clk,
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&main_clk,
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@ -267,6 +279,10 @@ static struct clk mstp_clks[MSTP_NR] = {
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static struct clk_lookup lookups[] = {
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/* main clocks */
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CLKDEV_CON_ID("audio_clk_a", &audio_clk_a),
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CLKDEV_CON_ID("audio_clk_b", &audio_clk_b),
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CLKDEV_CON_ID("audio_clk_c", &audio_clk_c),
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CLKDEV_CON_ID("audio_clk_internal", &m2_clk),
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CLKDEV_CON_ID("extal", &extal_clk),
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CLKDEV_CON_ID("extal_div2", &extal_div2_clk),
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CLKDEV_CON_ID("main", &main_clk),
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@ -312,34 +328,23 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
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CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
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CLKDEV_DEV_ID("e6508000.i2c", &mstp_clks[MSTP931]),
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CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
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CLKDEV_DEV_ID("e6518000.i2c", &mstp_clks[MSTP930]),
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CLKDEV_DEV_ID("i2c-rcar_gen2.1", &mstp_clks[MSTP930]),
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CLKDEV_DEV_ID("e6530000.i2c", &mstp_clks[MSTP929]),
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CLKDEV_DEV_ID("i2c-rcar_gen2.2", &mstp_clks[MSTP929]),
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CLKDEV_DEV_ID("e6540000.i2c", &mstp_clks[MSTP928]),
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CLKDEV_DEV_ID("i2c-rcar_gen2.3", &mstp_clks[MSTP928]),
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CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
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CLKDEV_DEV_ID("r8a7790-vin.0", &mstp_clks[MSTP811]),
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CLKDEV_DEV_ID("r8a7790-vin.1", &mstp_clks[MSTP810]),
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CLKDEV_DEV_ID("r8a7790-vin.2", &mstp_clks[MSTP809]),
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CLKDEV_DEV_ID("r8a7790-vin.3", &mstp_clks[MSTP808]),
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CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP502]),
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CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP501]),
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CLKDEV_DEV_ID("ee200000.mmc", &mstp_clks[MSTP315]),
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CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
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CLKDEV_DEV_ID("ee100000.sd", &mstp_clks[MSTP314]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
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CLKDEV_DEV_ID("ee120000.sd", &mstp_clks[MSTP313]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
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CLKDEV_DEV_ID("ee140000.sd", &mstp_clks[MSTP312]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP312]),
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CLKDEV_DEV_ID("ee160000.sd", &mstp_clks[MSTP311]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP311]),
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CLKDEV_DEV_ID("ee220000.mmc", &mstp_clks[MSTP305]),
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CLKDEV_DEV_ID("sh_mmcif.1", &mstp_clks[MSTP305]),
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CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
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CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
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@ -357,6 +362,10 @@ static struct clk_lookup lookups[] = {
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CLKDEV_ICK_ID("du.0", "rcar-du-r8a7790", &mstp_clks[MSTP724]),
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CLKDEV_ICK_ID("du.1", "rcar-du-r8a7790", &mstp_clks[MSTP723]),
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CLKDEV_ICK_ID("du.2", "rcar-du-r8a7790", &mstp_clks[MSTP722]),
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CLKDEV_ICK_ID("clk_a", "rcar_sound", &audio_clk_a),
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CLKDEV_ICK_ID("clk_b", "rcar_sound", &audio_clk_b),
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CLKDEV_ICK_ID("clk_c", "rcar_sound", &audio_clk_c),
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CLKDEV_ICK_ID("clk_i", "rcar_sound", &m2_clk),
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CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP1015]),
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CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP1014]),
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CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP1013]),
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@ -61,6 +61,7 @@
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#define MSTPSR1 IOMEM(0xe6150038)
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#define MSTPSR2 IOMEM(0xe6150040)
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#define MSTPSR3 IOMEM(0xe6150048)
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#define MSTPSR5 IOMEM(0xe615003c)
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#define MSTPSR7 IOMEM(0xe61501c4)
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#define MSTPSR8 IOMEM(0xe61509a0)
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@ -69,8 +70,8 @@
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#define MODEMR 0xE6160060
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#define SDCKCR 0xE6150074
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#define SD2CKCR 0xE6150078
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#define SD3CKCR 0xE615007C
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#define SD1CKCR 0xE6150078
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#define SD2CKCR 0xE615026c
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#define MMC0CKCR 0xE6150240
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#define MMC1CKCR 0xE6150244
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#define SSPCKCR 0xE6150248
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@ -101,6 +102,7 @@ static struct clk main_clk = {
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*/
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SH_FIXED_RATIO_CLK_SET(pll1_clk, main_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(pll3_clk, main_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(qspi_clk, pll1_clk, 1, 1);
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/* fixed ratio clock */
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SH_FIXED_RATIO_CLK_SET(extal_div2_clk, extal_clk, 1, 2);
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@ -124,6 +126,7 @@ static struct clk *main_clks[] = {
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&pll3_clk,
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&hp_clk,
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&p_clk,
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&qspi_clk,
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&rclk_clk,
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&mp_clk,
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&cp_clk,
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@ -132,15 +135,50 @@ static struct clk *main_clks[] = {
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&zs_clk,
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};
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/* SDHI (DIV4) clock */
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static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18, 24, 0, 36, 48, 10 };
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static struct clk_div_mult_table div4_div_mult_table = {
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.divisors = divisors,
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.nr_divisors = ARRAY_SIZE(divisors),
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};
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static struct clk_div4_table div4_table = {
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.div_mult_table = &div4_div_mult_table,
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};
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enum {
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DIV4_SDH, DIV4_SD0,
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DIV4_NR
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};
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static struct clk div4_clks[DIV4_NR] = {
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[DIV4_SDH] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 8, 0x0dff, CLK_ENABLE_ON_INIT),
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[DIV4_SD0] = SH_CLK_DIV4(&pll1_clk, SDCKCR, 4, 0x1de0, CLK_ENABLE_ON_INIT),
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};
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/* DIV6 clocks */
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enum {
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DIV6_SD1, DIV6_SD2,
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DIV6_NR
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};
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static struct clk div6_clks[DIV6_NR] = {
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[DIV6_SD1] = SH_CLK_DIV6(&pll1_div2_clk, SD1CKCR, 0),
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[DIV6_SD2] = SH_CLK_DIV6(&pll1_div2_clk, SD2CKCR, 0),
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};
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/* MSTP */
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enum {
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MSTP931, MSTP930, MSTP929, MSTP928, MSTP927, MSTP925,
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MSTP917,
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MSTP815, MSTP814,
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MSTP813,
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MSTP811, MSTP810, MSTP809,
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MSTP726, MSTP724, MSTP723, MSTP721, MSTP720,
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MSTP719, MSTP718, MSTP715, MSTP714,
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MSTP522,
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MSTP314, MSTP312, MSTP311,
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MSTP216, MSTP207, MSTP206,
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MSTP204, MSTP203, MSTP202, MSTP1105, MSTP1106, MSTP1107,
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MSTP124,
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@ -154,6 +192,7 @@ static struct clk mstp_clks[MSTP_NR] = {
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[MSTP928] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 28, MSTPSR9, 0), /* I2C3 */
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[MSTP927] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 27, MSTPSR9, 0), /* I2C4 */
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||||
[MSTP925] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR9, 25, MSTPSR9, 0), /* I2C5 */
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[MSTP917] = SH_CLK_MSTP32_STS(&qspi_clk, SMSTPCR9, 17, MSTPSR9, 0), /* QSPI */
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[MSTP815] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 15, MSTPSR8, 0), /* SATA0 */
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||||
[MSTP814] = SH_CLK_MSTP32_STS(&zs_clk, SMSTPCR8, 14, MSTPSR8, 0), /* SATA1 */
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[MSTP813] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR8, 13, MSTPSR8, 0), /* Ether */
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||||
|
|
@ -170,6 +209,9 @@ static struct clk mstp_clks[MSTP_NR] = {
|
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[MSTP715] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 15, MSTPSR7, 0), /* SCIF4 */
|
||||
[MSTP714] = SH_CLK_MSTP32_STS(&p_clk, SMSTPCR7, 14, MSTPSR7, 0), /* SCIF5 */
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||||
[MSTP522] = SH_CLK_MSTP32_STS(&extal_clk, SMSTPCR5, 22, MSTPSR5, 0), /* Thermal */
|
||||
[MSTP314] = SH_CLK_MSTP32_STS(&div4_clks[DIV4_SD0], SMSTPCR3, 14, MSTPSR3, 0), /* SDHI0 */
|
||||
[MSTP312] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD1], SMSTPCR3, 12, MSTPSR3, 0), /* SDHI1 */
|
||||
[MSTP311] = SH_CLK_MSTP32_STS(&div6_clks[DIV6_SD2], SMSTPCR3, 11, MSTPSR3, 0), /* SDHI2 */
|
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[MSTP216] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 16, MSTPSR2, 0), /* SCIFB2 */
|
||||
[MSTP207] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 7, MSTPSR2, 0), /* SCIFB1 */
|
||||
[MSTP206] = SH_CLK_MSTP32_STS(&mp_clk, SMSTPCR2, 6, MSTPSR2, 0), /* SCIFB0 */
|
||||
|
|
@ -195,6 +237,7 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_CON_ID("zs", &zs_clk),
|
||||
CLKDEV_CON_ID("hp", &hp_clk),
|
||||
CLKDEV_CON_ID("p", &p_clk),
|
||||
CLKDEV_CON_ID("qspi", &qspi_clk),
|
||||
CLKDEV_CON_ID("rclk", &rclk_clk),
|
||||
CLKDEV_CON_ID("mp", &mp_clk),
|
||||
CLKDEV_CON_ID("cp", &cp_clk),
|
||||
|
|
@ -219,7 +262,11 @@ static struct clk_lookup lookups[] = {
|
|||
CLKDEV_DEV_ID("sh-sci.12", &mstp_clks[MSTP1105]), /* SCIFA3 */
|
||||
CLKDEV_DEV_ID("sh-sci.13", &mstp_clks[MSTP1106]), /* SCIFA4 */
|
||||
CLKDEV_DEV_ID("sh-sci.14", &mstp_clks[MSTP1107]), /* SCIFA5 */
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP312]),
|
||||
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]),
|
||||
CLKDEV_DEV_ID("sh_cmt.0", &mstp_clks[MSTP124]),
|
||||
CLKDEV_DEV_ID("qspi.0", &mstp_clks[MSTP917]),
|
||||
CLKDEV_DEV_ID("e61f0000.thermal", &mstp_clks[MSTP522]),
|
||||
CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
|
||||
CLKDEV_DEV_ID("i2c-rcar_gen2.0", &mstp_clks[MSTP931]),
|
||||
|
|
@ -271,9 +318,20 @@ void __init r8a7791_clock_init(void)
|
|||
break;
|
||||
}
|
||||
|
||||
if ((mode & (MD(3) | MD(2) | MD(1))) == MD(2))
|
||||
SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 16);
|
||||
else
|
||||
SH_CLK_SET_RATIO(&qspi_clk_ratio, 1, 20);
|
||||
|
||||
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
||||
ret = clk_register(main_clks[k]);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_div6_register(div6_clks, DIV6_NR);
|
||||
|
||||
if (!ret)
|
||||
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
||||
|
||||
|
|
|
|||
|
|
@ -46,8 +46,8 @@
|
|||
#define R8A7790_CLK_MSIOF1 8
|
||||
#define R8A7790_CLK_MSIOF3 15
|
||||
#define R8A7790_CLK_SCIFB2 16
|
||||
#define R8A7790_CLK_SYS_DMAC0 18
|
||||
#define R8A7790_CLK_SYS_DMAC1 19
|
||||
#define R8A7790_CLK_SYS_DMAC1 18
|
||||
#define R8A7790_CLK_SYS_DMAC0 19
|
||||
|
||||
/* MSTP3 */
|
||||
#define R8A7790_CLK_TPU0 4
|
||||
|
|
|
|||
Loading…
Reference in New Issue