- Fix kernel panic on specific Qualcomm platform due to broken erratum
workaround - Revert contiguous bit support due to TLB conflict aborts in simulation - Don't treat all CPU ID register fields as 4-bit quantities -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCgAGBQJYsHbpAAoJELescNyEwWM03xgH/jPZwxdS0UL1WftjqE7VXBI2 5STwLBXB8cBr527QHBY7VCbtEQZAFnij7vJ8Eqe6nA8SMDbC1RTJ2ZkiPq0rKjVg pVJEdd3jEcRb3HNam90tOBTjlsyuR5Eagj0RI07j+YgsKhCxVTf6wu7z2StKhbuk o8P3fbV9JA9c68JR2MR7Z2GFe2pZW0vbRrKoSx6CdoCU8Wod46BUq+P+BoeVR+vZ 593ERXnDi9tzoWFLyJYobO0PVuoipjX4e6+NxX+hPRKck6gJByainhnl63gGil9L vavJ2r3GK4pO5qAsusx6eXQksyR9lX5tGPk7XgJi+M+WMd4Moe+/zNXd4NADGww= =aG7Y -----END PGP SIGNATURE----- Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Will Deacon: "The main fix here addresses a kernel panic triggered on Qualcomm QDF2400 due to incorrect register usage in an erratum workaround introduced during the merge window. Summary: - Fix kernel panic on specific Qualcomm platform due to broken erratum workaround - Revert contiguous bit support due to TLB conflict aborts in simulation - Don't treat all CPU ID register fields as 4-bit quantities" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64/cpufeature: check correct field width when updating sys_val Revert "arm64: mm: set the contiguous bit for kernel mappings where appropriate" arm64: Avoid clobbering mm in erratum workaround on QDF2400
This commit is contained in:
commit
6053dc9814
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@ -184,16 +184,22 @@ static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
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}
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}
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static inline int __attribute_const__
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static inline int __attribute_const__
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cpuid_feature_extract_field(u64 features, int field, bool sign)
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cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
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{
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{
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return (sign) ?
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return (sign) ?
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cpuid_feature_extract_signed_field(features, field) :
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cpuid_feature_extract_signed_field_width(features, field, width) :
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cpuid_feature_extract_unsigned_field(features, field);
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cpuid_feature_extract_unsigned_field_width(features, field, width);
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}
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static inline int __attribute_const__
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cpuid_feature_extract_field(u64 features, int field, bool sign)
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{
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return cpuid_feature_extract_field_width(features, field, 4, sign);
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}
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}
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static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
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static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
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{
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{
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return (s64)cpuid_feature_extract_field(val, ftrp->shift, ftrp->sign);
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return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
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}
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}
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static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
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static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
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@ -109,10 +109,8 @@ static bool pgattr_change_is_safe(u64 old, u64 new)
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static void alloc_init_pte(pmd_t *pmd, unsigned long addr,
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static void alloc_init_pte(pmd_t *pmd, unsigned long addr,
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unsigned long end, unsigned long pfn,
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unsigned long end, unsigned long pfn,
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pgprot_t prot,
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pgprot_t prot,
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phys_addr_t (*pgtable_alloc)(void),
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phys_addr_t (*pgtable_alloc)(void))
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bool page_mappings_only)
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{
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{
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pgprot_t __prot = prot;
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pte_t *pte;
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pte_t *pte;
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BUG_ON(pmd_sect(*pmd));
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BUG_ON(pmd_sect(*pmd));
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@ -130,18 +128,7 @@ static void alloc_init_pte(pmd_t *pmd, unsigned long addr,
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do {
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do {
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pte_t old_pte = *pte;
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pte_t old_pte = *pte;
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/*
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set_pte(pte, pfn_pte(pfn, prot));
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* Set the contiguous bit for the subsequent group of PTEs if
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* its size and alignment are appropriate.
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*/
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if (((addr | PFN_PHYS(pfn)) & ~CONT_PTE_MASK) == 0) {
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if (end - addr >= CONT_PTE_SIZE && !page_mappings_only)
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__prot = __pgprot(pgprot_val(prot) | PTE_CONT);
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else
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__prot = prot;
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}
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set_pte(pte, pfn_pte(pfn, __prot));
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pfn++;
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pfn++;
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/*
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/*
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@ -160,7 +147,6 @@ static void alloc_init_pmd(pud_t *pud, unsigned long addr, unsigned long end,
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phys_addr_t (*pgtable_alloc)(void),
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phys_addr_t (*pgtable_alloc)(void),
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bool page_mappings_only)
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bool page_mappings_only)
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{
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{
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pgprot_t __prot = prot;
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pmd_t *pmd;
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pmd_t *pmd;
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unsigned long next;
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unsigned long next;
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@ -187,18 +173,7 @@ static void alloc_init_pmd(pud_t *pud, unsigned long addr, unsigned long end,
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/* try section mapping first */
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/* try section mapping first */
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if (((addr | next | phys) & ~SECTION_MASK) == 0 &&
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if (((addr | next | phys) & ~SECTION_MASK) == 0 &&
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!page_mappings_only) {
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!page_mappings_only) {
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/*
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pmd_set_huge(pmd, phys, prot);
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* Set the contiguous bit for the subsequent group of
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* PMDs if its size and alignment are appropriate.
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*/
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if (((addr | phys) & ~CONT_PMD_MASK) == 0) {
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if (end - addr >= CONT_PMD_SIZE)
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__prot = __pgprot(pgprot_val(prot) |
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PTE_CONT);
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else
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__prot = prot;
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}
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pmd_set_huge(pmd, phys, __prot);
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/*
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/*
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* After the PMD entry has been populated once, we
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* After the PMD entry has been populated once, we
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@ -208,8 +183,7 @@ static void alloc_init_pmd(pud_t *pud, unsigned long addr, unsigned long end,
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pmd_val(*pmd)));
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pmd_val(*pmd)));
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} else {
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} else {
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alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys),
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alloc_init_pte(pmd, addr, next, __phys_to_pfn(phys),
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prot, pgtable_alloc,
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prot, pgtable_alloc);
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page_mappings_only);
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BUG_ON(pmd_val(old_pmd) != 0 &&
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BUG_ON(pmd_val(old_pmd) != 0 &&
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pmd_val(old_pmd) != pmd_val(*pmd));
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pmd_val(old_pmd) != pmd_val(*pmd));
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@ -138,7 +138,7 @@ ENDPROC(cpu_do_resume)
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* - pgd_phys - physical address of new TTB
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* - pgd_phys - physical address of new TTB
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*/
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*/
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ENTRY(cpu_do_switch_mm)
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ENTRY(cpu_do_switch_mm)
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pre_ttbr0_update_workaround x0, x1, x2
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pre_ttbr0_update_workaround x0, x2, x3
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mmid x1, x1 // get mm->context.id
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mmid x1, x1 // get mm->context.id
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bfi x0, x1, #48, #16 // set the ASID
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bfi x0, x1, #48, #16 // set the ASID
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msr ttbr0_el1, x0 // set TTBR0
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msr ttbr0_el1, x0 // set TTBR0
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