perf/x86/intel: Add Knights Mill CPUID
Add Knights Mill (KNM) to the list of CPUIDs supported by PMU. Signed-off-by: Piotr Luc <piotr.luc@intel.com> Reviewed-by: Dave Hansen <dave.hansen@intel.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Borislav Petkov <bp@alien8.de> Cc: Brian Gerst <brgerst@gmail.com> Cc: Denys Vlasenko <dvlasenk@redhat.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Josh Poimboeuf <jpoimboe@redhat.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20161012182634.2462-1-piotr.luc@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
parent
0047f59834
commit
608284bf0d
|
@ -3898,6 +3898,7 @@ __init int intel_pmu_init(void)
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case INTEL_FAM6_XEON_PHI_KNL:
|
case INTEL_FAM6_XEON_PHI_KNL:
|
||||||
|
case INTEL_FAM6_XEON_PHI_KNM:
|
||||||
memcpy(hw_cache_event_ids,
|
memcpy(hw_cache_event_ids,
|
||||||
slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
|
slm_hw_cache_event_ids, sizeof(hw_cache_event_ids));
|
||||||
memcpy(hw_cache_extra_regs,
|
memcpy(hw_cache_extra_regs,
|
||||||
|
@ -3912,7 +3913,7 @@ __init int intel_pmu_init(void)
|
||||||
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
|
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
|
||||||
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
|
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
|
||||||
|
|
||||||
pr_cont("Knights Landing events, ");
|
pr_cont("Knights Landing/Mill events, ");
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case INTEL_FAM6_SKYLAKE_MOBILE:
|
case INTEL_FAM6_SKYLAKE_MOBILE:
|
||||||
|
|
Loading…
Reference in New Issue