pinctrl: gemini: Implement clock skew/delay config
This enabled pin config on the Gemini driver and implements pin skew/delay so that the ethernet pins clocking can be properly configured. Acked-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
1c5b7f3c34
commit
60ad481f74
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@ -9,8 +9,14 @@ The pin controller node must be a subnode of the system controller node.
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Required properties:
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- compatible: "cortina,gemini-pinctrl"
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Subnodes of the pin controller contain pin control multiplexing set-up.
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Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes.
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Subnodes of the pin controller contain pin control multiplexing set-up
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and pin configuration of individual pins.
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Please refer to pinctrl-bindings.txt for generic pin multiplexing nodes
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and generic pin config nodes.
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Supported configurations:
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- skew-delay is supported on the Ethernet pins
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Example:
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@ -24,6 +24,19 @@
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#define DRIVER_NAME "pinctrl-gemini"
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/**
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* struct gemini_pin_conf - information about configuring a pin
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* @pin: the pin number
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* @reg: config register
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* @mask: the bits affecting the configuration of the pin
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*/
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struct gemini_pin_conf {
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unsigned int pin;
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u32 reg;
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u32 mask;
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};
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/**
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* struct gemini_pmx - state holder for the gemini pin controller
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* @dev: a pointer back to containing device
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* @virtbase: the offset to the controller in virtual memory
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* @map: regmap to access registers
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@ -31,6 +44,8 @@
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* @is_3516: whether the SoC/package is the 3516 variant
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* @flash_pin: whether the flash pin (extended pins for parallel
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* flash) is set
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* @confs: pin config information
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* @nconfs: number of pin config information items
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*/
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struct gemini_pmx {
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struct device *dev;
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@ -39,6 +54,8 @@ struct gemini_pmx {
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bool is_3512;
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bool is_3516;
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bool flash_pin;
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const struct gemini_pin_conf *confs;
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unsigned int nconfs;
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};
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/**
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@ -59,6 +76,13 @@ struct gemini_pin_group {
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u32 value;
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};
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/* Some straight-forward control registers */
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#define GLOBAL_WORD_ID 0x00
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#define GLOBAL_STATUS 0x04
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#define GLOBAL_STATUS_FLPIN BIT(20)
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#define GLOBAL_GMAC_CTRL_SKEW 0x1c
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#define GLOBAL_GMAC0_DATA_SKEW 0x20
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#define GLOBAL_GMAC1_DATA_SKEW 0x24
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/*
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* Global Miscellaneous Control Register
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* This register controls all Gemini pad/pin multiplexing
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@ -71,9 +95,6 @@ struct gemini_pin_group {
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* DISABLED again. So you select a flash configuration once, and then
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* you are stuck with it.
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*/
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#define GLOBAL_WORD_ID 0x00
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#define GLOBAL_STATUS 0x04
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#define GLOBAL_STATUS_FLPIN BIT(20)
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#define GLOBAL_MISC_CTRL 0x30
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#define TVC_CLK_PAD_ENABLE BIT(20)
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#define PCI_CLK_PAD_ENABLE BIT(17)
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@ -1925,7 +1946,7 @@ static const struct pinctrl_ops gemini_pctrl_ops = {
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.get_group_name = gemini_get_group_name,
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.get_group_pins = gemini_get_group_pins,
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.pin_dbg_show = gemini_pin_dbg_show,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_group,
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.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
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.dt_free_map = pinconf_generic_dt_free_map,
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};
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@ -2203,10 +2224,155 @@ static const struct pinmux_ops gemini_pmx_ops = {
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.set_mux = gemini_pmx_set_mux,
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};
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#define GEMINI_CFGPIN(_n, _r, _lb, _hb) { \
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.pin = _n, \
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.reg = _r, \
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.mask = GENMASK(_hb, _lb) \
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}
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static const struct gemini_pin_conf gemini_confs_3512[] = {
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GEMINI_CFGPIN(259, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
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GEMINI_CFGPIN(277, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
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GEMINI_CFGPIN(241, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
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GEMINI_CFGPIN(312, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
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GEMINI_CFGPIN(298, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
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GEMINI_CFGPIN(280, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
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GEMINI_CFGPIN(316, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
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GEMINI_CFGPIN(243, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
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GEMINI_CFGPIN(295, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
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GEMINI_CFGPIN(313, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
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GEMINI_CFGPIN(242, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
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GEMINI_CFGPIN(260, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
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GEMINI_CFGPIN(294, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
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GEMINI_CFGPIN(276, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
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GEMINI_CFGPIN(258, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
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GEMINI_CFGPIN(240, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
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GEMINI_CFGPIN(262, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
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GEMINI_CFGPIN(244, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
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GEMINI_CFGPIN(317, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
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GEMINI_CFGPIN(299, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
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GEMINI_CFGPIN(261, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
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GEMINI_CFGPIN(279, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
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GEMINI_CFGPIN(297, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
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GEMINI_CFGPIN(315, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
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};
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static const struct gemini_pin_conf gemini_confs_3516[] = {
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GEMINI_CFGPIN(347, GLOBAL_GMAC_CTRL_SKEW, 0, 3), /* GMAC0 RXDV */
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GEMINI_CFGPIN(386, GLOBAL_GMAC_CTRL_SKEW, 4, 7), /* GMAC0 RXC */
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GEMINI_CFGPIN(307, GLOBAL_GMAC_CTRL_SKEW, 8, 11), /* GMAC0 TXEN */
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GEMINI_CFGPIN(327, GLOBAL_GMAC_CTRL_SKEW, 12, 15), /* GMAC0 TXC */
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GEMINI_CFGPIN(309, GLOBAL_GMAC_CTRL_SKEW, 16, 19), /* GMAC1 RXDV */
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GEMINI_CFGPIN(390, GLOBAL_GMAC_CTRL_SKEW, 20, 23), /* GMAC1 RXC */
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GEMINI_CFGPIN(370, GLOBAL_GMAC_CTRL_SKEW, 24, 27), /* GMAC1 TXEN */
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GEMINI_CFGPIN(350, GLOBAL_GMAC_CTRL_SKEW, 28, 31), /* GMAC1 TXC */
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GEMINI_CFGPIN(367, GLOBAL_GMAC0_DATA_SKEW, 0, 3), /* GMAC0 RXD0 */
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GEMINI_CFGPIN(348, GLOBAL_GMAC0_DATA_SKEW, 4, 7), /* GMAC0 RXD1 */
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GEMINI_CFGPIN(387, GLOBAL_GMAC0_DATA_SKEW, 8, 11), /* GMAC0 RXD2 */
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GEMINI_CFGPIN(328, GLOBAL_GMAC0_DATA_SKEW, 12, 15), /* GMAC0 RXD3 */
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GEMINI_CFGPIN(306, GLOBAL_GMAC0_DATA_SKEW, 16, 19), /* GMAC0 TXD0 */
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GEMINI_CFGPIN(325, GLOBAL_GMAC0_DATA_SKEW, 20, 23), /* GMAC0 TXD1 */
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GEMINI_CFGPIN(346, GLOBAL_GMAC0_DATA_SKEW, 24, 27), /* GMAC0 TXD2 */
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GEMINI_CFGPIN(326, GLOBAL_GMAC0_DATA_SKEW, 28, 31), /* GMAC0 TXD3 */
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GEMINI_CFGPIN(391, GLOBAL_GMAC1_DATA_SKEW, 0, 3), /* GMAC1 RXD0 */
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GEMINI_CFGPIN(351, GLOBAL_GMAC1_DATA_SKEW, 4, 7), /* GMAC1 RXD1 */
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GEMINI_CFGPIN(310, GLOBAL_GMAC1_DATA_SKEW, 8, 11), /* GMAC1 RXD2 */
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GEMINI_CFGPIN(371, GLOBAL_GMAC1_DATA_SKEW, 12, 15), /* GMAC1 RXD3 */
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GEMINI_CFGPIN(329, GLOBAL_GMAC1_DATA_SKEW, 16, 19), /* GMAC1 TXD0 */
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GEMINI_CFGPIN(389, GLOBAL_GMAC1_DATA_SKEW, 20, 23), /* GMAC1 TXD1 */
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GEMINI_CFGPIN(369, GLOBAL_GMAC1_DATA_SKEW, 24, 27), /* GMAC1 TXD2 */
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GEMINI_CFGPIN(308, GLOBAL_GMAC1_DATA_SKEW, 28, 31), /* GMAC1 TXD3 */
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};
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static const struct gemini_pin_conf *gemini_get_pin_conf(struct gemini_pmx *pmx,
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unsigned int pin)
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{
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const struct gemini_pin_conf *retconf;
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int i;
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for (i = 0; i < pmx->nconfs; i++) {
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retconf = &gemini_confs_3516[i];
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if (retconf->pin == pin)
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return retconf;
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}
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return NULL;
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}
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static int gemini_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *config)
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{
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struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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enum pin_config_param param = pinconf_to_config_param(*config);
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const struct gemini_pin_conf *conf;
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u32 val;
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switch (param) {
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case PIN_CONFIG_SKEW_DELAY:
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conf = gemini_get_pin_conf(pmx, pin);
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if (!conf)
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return -ENOTSUPP;
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regmap_read(pmx->map, conf->reg, &val);
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val &= conf->mask;
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val >>= (ffs(conf->mask) - 1);
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*config = pinconf_to_config_packed(PIN_CONFIG_SKEW_DELAY, val);
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break;
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default:
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return -ENOTSUPP;
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}
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return 0;
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}
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static int gemini_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned long *configs, unsigned int num_configs)
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{
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struct gemini_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
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const struct gemini_pin_conf *conf;
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enum pin_config_param param;
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u32 arg;
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int ret = 0;
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int i;
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for (i = 0; i < num_configs; i++) {
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param = pinconf_to_config_param(configs[i]);
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arg = pinconf_to_config_argument(configs[i]);
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switch (param) {
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case PIN_CONFIG_SKEW_DELAY:
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if (arg > 0xf)
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return -EINVAL;
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conf = gemini_get_pin_conf(pmx, pin);
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if (!conf) {
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dev_err(pmx->dev,
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"invalid pin for skew delay %d\n", pin);
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return -ENOTSUPP;
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}
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arg <<= (ffs(conf->mask) - 1);
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dev_dbg(pmx->dev,
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"set pin %d to skew delay mask %08x, val %08x\n",
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pin, conf->mask, arg);
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regmap_update_bits(pmx->map, conf->reg, conf->mask, arg);
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break;
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default:
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dev_err(pmx->dev, "Invalid config param %04x\n", param);
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return -ENOTSUPP;
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}
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}
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return ret;
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}
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static const struct pinconf_ops gemini_pinconf_ops = {
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.pin_config_get = gemini_pinconf_get,
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.pin_config_set = gemini_pinconf_set,
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.is_generic = true,
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};
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static struct pinctrl_desc gemini_pmx_desc = {
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.name = DRIVER_NAME,
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.pctlops = &gemini_pctrl_ops,
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.pmxops = &gemini_pmx_ops,
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.confops = &gemini_pinconf_ops,
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.owner = THIS_MODULE,
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};
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@ -2249,11 +2415,15 @@ static int gemini_pmx_probe(struct platform_device *pdev)
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val &= 0xffff;
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if (val == 0x3512) {
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pmx->is_3512 = true;
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pmx->confs = gemini_confs_3512;
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pmx->nconfs = ARRAY_SIZE(gemini_confs_3512);
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gemini_pmx_desc.pins = gemini_3512_pins;
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gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3512_pins);
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dev_info(dev, "detected 3512 chip variant\n");
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} else if (val == 0x3516) {
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pmx->is_3516 = true;
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pmx->confs = gemini_confs_3516;
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pmx->nconfs = ARRAY_SIZE(gemini_confs_3516);
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gemini_pmx_desc.pins = gemini_3516_pins;
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gemini_pmx_desc.npins = ARRAY_SIZE(gemini_3516_pins);
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dev_info(dev, "detected 3516 chip variant\n");
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